📄 rc500.lst
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469 2 case 2: // medium timeout (1,5 ms)
470 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
471 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
472 2 break;
473 2 case 3: // medium timeout (6 ms)
474 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
475 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
476 2 break;
477 2 case 4: // long timeout (9.6 ms)
478 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
479 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
480 2 break;
481 2 case 5: // long timeout (38.5 ms)
482 2 WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
483 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
484 2 break;
485 2 case 6: // long timeout (154 ms)
486 2 WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
487 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
488 2 break;
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 9
489 2 case 7: // long timeout (616.2 ms)
490 2 WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
491 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
492 2 break;
493 2 default: //
494 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
495 2 WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
496 2 break;
497 2 }
498 1 TOGGLE_WD();
499 1 }
500
501 //////////////////////////////////////////////////////////////////////
502 // W R I T E A P C D C O M M A N D
503 ///////////////////////////////////////////////////////////////////////
504 char M500PcdCmd(unsigned char cmd,
505 volatile unsigned char * send, /*pan add*/
506 volatile unsigned char * rcv,
507 volatile MfCmdInfo *info)
508 {
509 1 char idata status = MI_OK;
510 1 char idata tmpStatus ;
511 1 unsigned char idata lastBits;
512 1
513 1 unsigned char idata irqEn = 0x00;
514 1 unsigned char idata waitFor = 0x00;
515 1 unsigned char idata timerCtl = 0x00;
516 1 TOGGLE_WD();
517 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
518 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
519 1 WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
520 1
521 1 FlushFIFO(); // flush FIFO buffer
522 1
523 1 // save info structures to module pointers
524 1 MpIsrInfo = info;
525 1 MpIsrOut = send;
526 1 MpIsrIn = rcv;
527 1 //pan add i=MpIsrOut[0];
528 1 info->irqSource = 0x0; // reset interrupt flags
529 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
530 1 // and the commit interrupt is choosen (waitFor).
531 1 switch(cmd)
532 1 {
533 2 case PCD_IDLE: // nothing else required
534 2 irqEn = 0x00;
535 2 waitFor = 0x00;
536 2 break;
537 2 case PCD_WRITEE2: // LoAlert and TxIRq
538 2 irqEn = 0x11;
539 2 waitFor = 0x10;
540 2 break;
541 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq
542 2 irqEn = 0x07;
543 2 waitFor = 0x04;
544 2 break;
545 2 case PCD_LOADCONFIG: // IdleIRq
546 2 case PCD_LOADKEYE2: // IdleIRq
547 2 case PCD_AUTHENT1: // IdleIRq
548 2 irqEn = 0x05;
549 2 waitFor = 0x04;
550 2 break;
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 10
551 2 case PCD_CALCCRC: // LoAlert and TxIRq
552 2 irqEn = 0x11;
553 2 waitFor = 0x10;
554 2 break;
555 2 case PCD_AUTHENT2: // IdleIRq
556 2 irqEn = 0x04;
557 2 waitFor = 0x04;
558 2 break;
559 2 case PCD_RECEIVE: // HiAlert and IdleIRq
560 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
561 2 irqEn = 0x06;
562 2 waitFor = 0x04;
563 2 break;
564 2 case PCD_LOADKEY: // IdleIRq
565 2 irqEn = 0x05;
566 2 waitFor = 0x04;
567 2 break;
568 2 case PCD_TRANSMIT: // LoAlert and IdleIRq
569 2 irqEn = 0x05;
570 2 waitFor = 0x04;
571 2 break;
572 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
573 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
574 2 irqEn = 0x3D;
575 2 waitFor = 0x04;
576 2 break;
577 2 default:
578 2 status = MI_UNKNOWN_COMMAND;
579 2 }
580 1 if (status == MI_OK)
581 1 {
582 2 // Initialize uC Timer for global Timeout management
583 2 irqEn |= 0x20; // always enable timout irq
584 2 waitFor |= 0x20; // always wait for timeout
585 2
586 2 start_timeout(4000); // initialise and start guard timer for reader
587 2 // 50us resolution, 200ms
588 2
589 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
590 2 WriteIO(RegCommand,cmd); //start command
591 2
592 2 // wait for commmand completion
593 2 // a command is completed, if the corresponding interrupt occurs
594 2 // or a timeout is signaled
595 2
596 2 while (!(MpIsrInfo->irqSource & waitFor
597 2 || T2IR)) TOGGLE_WD(); // wait for cmd completion or timeout
598 2
599 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
600 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
601 2 SetBitMask(RegControl,0x04); // stop timer now
602 2
603 2 stop_timeout(); // stop timeout for reader
604 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
605 2
606 2
607 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
608 2 { // timer 2 expired
609 3 status = MI_ACCESSTIMEOUT;
610 3 }
611 2 else
612 2 status = MpIsrInfo->status; // set status
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 11
613 2
614 2 if (status == MI_OK) // no timeout error occured
615 2 {
616 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
617 3 {
618 4 if (tmpStatus & 0x01) // collision detected
619 4 {
620 5 info->collPos = ReadIO(RegCollpos); // read collision position
621 5 status = MI_COLLERR;
622 5 }
623 4 else
624 4 {
625 5 info->collPos = 0;
626 5 if (tmpStatus & 0x02) // parity error
627 5 {
628 6 status = MI_PARITYERR;
629 6 }
630 5 }
631 4 if (tmpStatus & 0x04) // framing error
632 4 {
633 5 status = MI_FRAMINGERR;
634 5 }
635 4 if (tmpStatus & 0x10) // FIFO overflow
636 4 {
637 5 FlushFIFO();
638 5 status = MI_OVFLERR;
639 5 }
640 4 if (tmpStatus & 0x08) //CRC error
641 4 {
642 5 status = MI_CRCERR;
643 5 }
644 4 if (status == MI_OK)
645 4 status = MI_NY_IMPLEMENTED;
646 4 // key error occures always, because of
647 4 // missing crypto 1 keys loaded
648 4 }
649 3 // if the last command was TRANSCEIVE, the number of
650 3 // received bits must be calculated - even if an error occured
651 3 if (cmd == PCD_TRANSCEIVE)
652 3 {
653 4 // number of bits in the last byte
654 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
655 4 if (lastBits)
656 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
657 4 else
658 4 info->nBitsReceived += info->nBytesReceived * 8;
659 4 }
660 3 }
661 2 else
662 2 {
663 3 info->collPos = 0x00;
664 3 }
665 2 }
666 1 MpIsrInfo = 0; // reset interface variables for ISR
667 1 MpIsrOut = 0;
668 1 MpIsrIn = 0;
669 1 TOGGLE_WD();
670 1 return status;
671 1
672 1 }
673
674 //////////////////////////////////////////////////////////////////////
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 12
675 // S E T A B I T M A S K
676 ///////////////////////////////////////////////////////////////////////
677 char SetBitMask(unsigned char reg,unsigned char mask) //
678 {
679 1 char idata tmp = 0x0;
680 1 TOGGLE_WD();
681 1 tmp = ReadIO(reg);
682 1 WriteIO(reg,tmp | mask); // set bit mask
683 1 TOGGLE_WD();
684 1 return 0x0;
685 1 }
686
687 //////////////////////////////////////////////////////////////////////
688 // C L E A R A B I T M A S K
689 ///////////////////////////////////////////////////////////////////////
690 char ClearBitMask(unsigned char reg,unsigned char mask) //
691 {
692 1 char idata tmp = 0x0;
693 1
694 1 tmp = ReadIO(reg);
695 1 WriteIO(reg,tmp & ~mask); // clear bit mask
696 1 return 0x0;
697 1 }
698
699 ///////////////////////////////////////////////////////////////////////
700 // F L U S H F I F O
701 ///////////////////////////////////////////////////////////////////////
702 void FlushFIFO(void)
703 {
704 1 SetBitMask(RegControl,0x01);
705 1 }
706
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