📄 rc500.lst
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231
232 // _____________________________________________________________________________
233 //
234 // FUNCTION: M500PcdSetTmo
235 // IN: tmoLength 1 ... 1.0 ms timeout periode
236 // 2 ... 1.5 ms timeout periode
237 // 3 ... 6.0 ms timeout periode
238 // 4 ... 9.6 ms timeout period
239 // 5 ... 38.5 ms timeout period
240 // 6 ... 154 ms timeout period
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 5
241 // 7 ... 616.2 ms timeout period
242 // OUT: -
243 // RETURN:
244 // COMMENT: Set timeout length of the reader internal timer.
245 //
246 void M500PcdSetTmo(unsigned char tmoLength);
247
248 // _____________________________________________________________________________
249 //
250 // FUNCTION: M500PcdCmd
251 // IN: cmd PCD_IDLE
252 // PCD_WRITEE2
253 // PCD_READE2
254 // PCD_LOADCONFIG
255 // PCD_LOADKEYE2
256 // PCD_AUTHENT1
257 // PCD_CALCCRC
258 // PCD_AUTHENT2
259 // PCD_RECEIVE
260 // PCD_LOADKEY
261 // PCD_TRANSMIT
262 // PCD_TRANSCEIVE
263 // PCD_RESETPHASE
264 // for a detailed description of the parameter values, please
265 // have a look on the header file of the reader register
266 // definitions.
267 // send byte stream of variable length, which should be send to
268 // the PICC, the length of stream has to be specified
269 // in the info - structure
270 // OUT: rcv byte stream of variable length, which was received
271 // from the PICC or PCD
272 // info communication and status structure
273 // RETURN:
274 // COMMENT: This function provides the central interface to the reader module.
275 // Depending on the "cmd"-value, all necessary interrupts are enabled
276 // and the communication is started. While the processing is done by
277 // the reader module, this function waits for its completion.
278 // It's notable, that the data in the "send byte stream" is written
279 // to the FIFO of the reader module by the ISR. Immediate after
280 // enabling the interrupts, the LoAlert interrupt is activated.
281 // The ISR writes the data to the FIFO. This function is not involved
282 // in writing or fetching data from FIFO, all work is done by the
283 // ISR.After command completion, the error status is evaluated and
284 // returned to the calling function.
285 //
286 char M500PcdCmd(unsigned char cmd,
287 volatile unsigned char * send, /*pan add*/
288 volatile unsigned char * rcv,
289 volatile MfCmdInfo *info);
290
291 // _____________________________________________________________________________
292 //
293 // FUNCTION: SetBitMask
294 // IN: reg register address
295 // mask bit mask to set
296 // OUT: -
297 // RETURN:
298 // COMMENT: This function performs a read - modify - write sequence
299 // on the specified register. All bits with a 1 in the mask
300 // are set - all other bits keep their original value.
301 //
302 char SetBitMask(unsigned char reg,unsigned char mask);
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 6
303
304 // _____________________________________________________________________________
305 //
306 // FUNCTION: ClearBitMask
307 // IN: reg register address
308 // mask bit mask to clear
309 // OUT: -
310 // RETURN:
311 // COMMENT: This function performs a read - modify - write sequence
312 // on the specified register. All bits with a 1 in the mask
313 // are cleared - all other bits keep their original value.
314 //
315 char ClearBitMask(unsigned char reg,unsigned char mask);
316
317 // _____________________________________________________________________________
318 //
319 // FUNCTION: FlushFIFO
320 // IN: -
321 // OUT: -
322 // RETURN:
323 // COMMENT: All remaining date in the FIFO of the reader module is
324 // erased by this function. Before wrinting new data or
325 // starting a new command, all remaining data from former
326 // commands should be deleted. Please note, that in
327 // normal operation, never data should be left, that means
328 // that a call to this function should not be necessary.
329 //
330 void FlushFIFO(void);
331
332 // _____________________________________________________________________________
333 //
334 // FUNCTION: M500PiccAuthState
335 // IN: auth_mode
336 // snr
337 // sector
338 // OUT: -
339 // RETURN:
340 // COMMENT:
341 //
342 char M500PiccAuthState(unsigned char auth_mode,// PICC_AUTHENT1A, PICC_AUTHENT1B
343 unsigned char *snr, // 4 byte serial number
344 unsigned char sector); // 0 <= sector <= 15
345 // sector address for authentication
346
347 //////////////////////////////////////////////////////////////////////
348 // E X C H A N G E B Y T E S T R E A M
349 ///////////////////////////////////////////////////////////////////////
350 char ExchangeByteStream(unsigned char Cmd,
351 unsigned char *send_data,
352 unsigned char send_bytelen,
353 unsigned char *rec_data,
354 unsigned char *rec_bytelen);
355
356 ///////////////////////////////////////////////////////////////////////////////
357 // Interrupt Handler RC500
358 ///////////////////////////////////////////////////////////////////////////////
359 void RC500ISR (void) interrupt 0 using 1 //Ext0 interrupt
360 {
361 1 static unsigned char idata irqBits;
362 1 static unsigned char idata irqMask;
363 1 static unsigned char idata nbytes;
364 1 static unsigned char idata cnt;
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 7
365 1 TOGGLE_WD();
366 1 IE0 = 0; // Clear interrupt request flag
367 1
368 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
369 1 // correctly
370 1 {
371 2 while( ReadRawIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
372 2 // Attention: IRQ bit is
373 2 // inverted when used with
374 2 // low activ IRQ
375 2 { TOGGLE_WD();
376 3 irqMask = ReadRawIO(RegInterruptEn); // read enabled interrupts
377 3 // read pending interrupts
378 3 irqBits = ReadRawIO(RegInterruptRq) & irqMask;
379 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
380 3 //************ LoAlertIRQ ******************
381 3 if (irqBits & 0x01) // LoAlert
382 3 {
383 4 nbytes = MFIFOLength - ReadRawIO(RegFIFOLength);
384 4 // less bytes to send, than space in FIFO
385 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
386 4 {
387 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
388 5 WriteRawIO(RegInterruptEn,0x01); // disable LoAlert IRQ
389 5 }
390 4 // write remaining data to the FIFO
391 4 for ( cnt = 0;cnt < nbytes;cnt++)
392 4 {
393 5 WriteRawIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
394 5 MpIsrInfo->nBytesSent++;
395 5 }
396 4 WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
397 4 }
398 3
399 3 //************* TxIRQ Handling **************
400 3 if (irqBits & 0x10) // TxIRQ
401 3 {
402 4 WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
403 4 WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
404 4 // response
405 4
406 4 if (((MpIsrInfo->cmd & 0xF0) == 0x90) // if cmd is anticollision
407 4 && (MpIsrInfo->nBitsReceived == 7)) // and 7 bits are known
408 4 { // switch off parity generation
409 5 WriteRawIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
410 5 }
411 4 }
412 3
413 3 //************* HiAlertIRQ or RxIRQ Handling ******************
414 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
415 3 {
416 4 // read some bytes ( length of FIFO queue)
417 4 // into the receive buffer
418 4 nbytes = ReadRawIO(RegFIFOLength);
419 4 // read date from the FIFO and store them in the receive buffer
420 4 for ( cnt = 0; cnt < nbytes; cnt++)
421 4 {
422 5 MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
423 5 MpIsrInfo->nBytesReceived++;
424 5 }
425 4 WriteRawIO(RegInterruptRq,0x0A & irqBits);
426 4 // reset IRQ bit - idle irq will
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 8
427 4 // be deleted in a seperate section
428 4 }
429 3
430 3 //************** IdleIRQ Handling ***********
431 3 if (irqBits & 0x04) // Idle IRQ
432 3 {
433 4 WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
434 4 WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
435 4 irqBits &= ~0x20; // clear Timer IRQ in local var
436 4 MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
437 4 // when idle received, then cancel
438 4 // timeout
439 4 WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
440 4 // status should still be MI_OK
441 4 // no error - only used for wake up
442 4 }
443 3
444 3 //************* TimerIRQ Handling ***********
445 3 if (irqBits & 0x20) // timer IRQ
446 3 {
447 4 WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
448 4 MpIsrInfo->status = MI_NOTAGERR; // timeout error
449 4 // otherwise ignore the interrupt
450 4 }
451 3
452 3 }
453 2 }
454 1 TOGGLE_WD();
455 1 }
456
457 ///////////////////////////////////////////////////////////////////////
458 // S e t T i m e o u t L E N G T H
459 ///////////////////////////////////////////////////////////////////////
460 void M500PcdSetTmo(unsigned char tmoLength)
461 {
462 1 TOGGLE_WD();
463 1 switch(tmoLength)
464 1 { // timer clock frequency 13,56 MHz
465 2 case 1: // short timeout (1,0 ms)
466 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
467 2 WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
468 2 break;
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