hw.c

VIA Framebuffer driver

    lock_crt();
    write_reg_mask(CR17, VIACR, 0x80, BIT7);
    load_offset_reg(h_addr, bpp_byte, set_iga);
    load_fetch_count_reg(h_addr, bpp_byte, set_iga);
    
    // load FIFO
    if ( (chip_info.gfx_chip_name != UNICHROME_CLE266) && (chip_info.gfx_chip_name != UNICHROME_K400))
        load_FIFO_reg(set_iga, h_addr, v_addr); 
        
    // load SR Register About Memory and Color part
    switch(bpp_byte) {
        case MODE_8BPP:
            write_reg_mask(SR15, VIASR, 0x22, 0xFE);
            break;
        case MODE_16BPP:
            write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
            break;
        case MODE_32BPP:
            write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
            break;
        
    }
    pll_D_N = get_clk_value(crt_table[index].clk);
    DEBUG_MSG( KERN_INFO "PLL=%x", pll_D_N);
    SetVCLK(pll_D_N, set_iga);		

}

void init_chip_info(void)
{
    init_gfx_chip_info(); 
    init_tv_chip_info();
    init_tmds_chip_info();
    init_lvds_chip_info(); 
    
    crt_setting_info.iga_path = IGA1; 
    //crt_setting_info.h_active = 1024;
    //crt_setting_info.v_active = 768;
    //crt_setting_info.bpp = bpp;
    crt_setting_info.refresh_rate = refresh;
    
    
    tv_setting_info.iga_path = IGA1; 
    tv_setting_info.level = tv_level;
    tv_setting_info.system = tv_system;
    tv_setting_info.out_signal = tv_out_signal;
    tv_setting_info.dedotcrawl = tv_dedotcrawl;
    
    tmds_setting_info.iga_path = IGA1; 
    //tmds_setting_info.h_active = 1024;
    //tmds_setting_info.v_active = 768;
    //tmds_setting_info.bpp = bpp;
    //tmds_setting_info.refresh_rate = refresh;
    
    lvds_setting_info.iga_path = IGA1; 
    //tmds_setting_info.h_active = 1024;
    //tmds_setting_info.v_active = 768;
    //tmds_setting_info.bpp = bpp;
    //tmds_setting_info.refresh_rate = refresh;
    
    DEBUG_MSG(KERN_INFO "TV= %2d\n", chip_info.tv_chip_info.tv_chip_name); 
    DEBUG_MSG(KERN_INFO "TV_SLAVE_ADDR= %2d\n", chip_info.tv_chip_info.tv_chip_slave_addr);
}

void update_device_setting(int hres, int vres, int bpp, int vmode_refresh)
{
    crt_setting_info.h_active = hres;
    crt_setting_info.v_active = vres;
    crt_setting_info.bpp = bpp;
    crt_setting_info.refresh_rate = vmode_refresh;
    
    tv_setting_info.h_active = hres;
    tv_setting_info.v_active = vres;
    tv_setting_info.bpp = bpp;    
       
    tmds_setting_info.h_active = hres;
    tmds_setting_info.v_active = vres;
    tmds_setting_info.bpp = bpp;
    tmds_setting_info.refresh_rate = vmode_refresh;
    
    lvds_setting_info.h_active = hres;
    lvds_setting_info.v_active = vres;
    lvds_setting_info.bpp = bpp;
    lvds_setting_info.refresh_rate = vmode_refresh;
}

void init_gfx_chip_info(void)
{
    struct pci_dev *pdev=NULL;
    u8     tmp; 
 
    // Indentify GFX Chip Name
    pdev = (struct pci_dev *)pci_find_device(UNICHROME_CLE266_VID, UNICHROME_CLE266_DID, NULL);
    if (pdev != NULL)
        chip_info.gfx_chip_name = UNICHROME_CLE266;
 
    pdev = (struct pci_dev *)pci_find_device(UNICHROME_K400_VID, UNICHROME_K400_DID, NULL);
    if (pdev != NULL)
        chip_info.gfx_chip_name = UNICHROME_K400;
           
    pdev = (struct pci_dev *)pci_find_device(UNICHROME_K800_VID, UNICHROME_K800_DID, NULL);
    if (pdev != NULL)
        chip_info.gfx_chip_name = UNICHROME_K800; 
    
    pdev = (struct pci_dev *)pci_find_device(UNICHROME_P880_VID, UNICHROME_P880_DID, NULL);
    if (pdev != NULL)
        chip_info.gfx_chip_name = UNICHROME_P880;
    
    
    // Check revision of CLE266 Chip 
    if (chip_info.gfx_chip_name == UNICHROME_CLE266)
    {
        // CR4F only define in CLE266.CX chip    
        tmp = read_reg(VIACR, CR4F);
        write_reg(CR4F, VIACR, 0x55);           
        if (read_reg(VIACR,CR4F)!=0x55)
            chip_info.gfx_chip_revision = CLE266_REVISION_AX;
        else
            chip_info.gfx_chip_revision = CLE266_REVISION_CX;

        write_reg(CR4F, VIACR, tmp);           // restore orignal CR4F value    
    }                      
}

void init_tv_chip_info(void)
{
    u8  data;
    
    tv_encoder_identify();
    data = read_reg(VIASR, SR12) & BIT5; // HW strapping: 0: TV on AMR 1: TV on AGP
    if ((chip_info.gfx_chip_name == UNICHROME_CLE266) || (data == 0x20))
    {
        chip_info.tv_chip_info.tv_chip_on_slot = TV_ON_AMR;
        chip_info.tv_chip_info.output_interface = INTERFACE_DVP0;    
    }
    else
    {
        chip_info.tv_chip_info.tv_chip_on_slot = TV_ON_AGP;
        data = read_reg(VIASR, SR12) & BIT4; // HW strapping: 0: 12-bits DVI 1: 24-bit Panel 
        if (data == 0x10)
            chip_info.tv_chip_info.output_interface = INTERFACE_DFP_LOW;
        else
            chip_info.tv_chip_info.output_interface = INTERFACE_DFP_HIGH;    
    }        
            
}

void init_tmds_chip_info(void)
{
    // set DVP1 default for DVI
    chip_info.tmds_chip_info.output_interface = INTERFACE_DVP1; 
    tmds_trasmitter_identify();
    DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", chip_info.tmds_chip_info.tmds_chip_name);
    init_dvi_size();
}

void init_lvds_chip_info(void)
{
    lvds_trasmitter_identify();
    DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", chip_info.tmds_chip_info.tmds_chip_name);
    init_lcd_size();
}

void init_dac(int set_iga)
{
    int i;
    u8 tmp;

    if (set_iga == IGA1)
    {
        write_reg_mask(SR1A, VIASR, 0x00, BIT0);        // access Primary Display's LUT 
        write_reg_mask(SR1B, VIASR, 0x00, BIT7+BIT6);   // turn off LCK
        for(i=0; i<256; i++)
        {
            write_dac_reg(i, palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue);     
        }
        
        write_reg_mask(SR1B, VIASR, 0xC0, BIT7+BIT6);   // turn on LCK
    }
    else
    {
	    tmp=read_reg(VIACR, CR6A);
        write_reg_mask(CR6A, VIACR, 0x40, BIT6); 	
        write_reg_mask(SR1A, VIASR, 0x01, BIT0);        // access Secondary Display's LUT 
        for(i=0; i<256; i++)
        {
            write_dac_reg(i, palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue);     
        }               
       write_reg_mask(SR1A, VIASR, 0x00, BIT0);        // set IGA1 DAC for default
       write_reg(CR6A, VIACR, tmp);	       
    }
}

void device_screen_off(void)
{
    if (CRT_ON==1){
        write_reg_mask(SR01, VIASR, 0x20, BIT5);   // turn off CRT screen (IGA1)    
    }
    if (TV_ON==1){
    }
    if (DVI_ON==1){
    }
    if (LCD_ON==1){
    }
}

void device_screen_on(void)
{
    if (CRT_ON==1){
        write_reg_mask(SR01, VIASR, 0x00, BIT5);   // turn on CRT screen (IGA1)    
    }
    if (TV_ON==1){
    }
    if (DVI_ON==1){
    }
    if (LCD_ON==1){
    }
}

int setmode(int vmode_index,int hor_res,int ver_res,int video_bpp)
{
     int i,j;
     int port;
     u8 value,index,mask;
     struct VideoModeTable      *vmode_tbl;
     struct crt_mode_table	*crt_timing;		

     DEBUG_MSG(KERN_INFO "Set Mode!!\n");
     DEBUG_MSG(KERN_INFO "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n", vmode_index, hor_res, ver_res, video_bpp);
     
     device_screen_off();
     vmode_tbl = &CLE266Modes[SearchModeSetting(vmode_index)];
     crt_timing = vmode_tbl->crtc;  
     inb(VIAStatus);
     outb(0x00,VIAAR);
  /* Write Common Setting for Video Mode */
     WriteRegX( CLE266_ModeXregs,NUM_TOTAL_ModeXregs );

  /* Fill VPIT Parameters */
  // Write Misc Register
     outb(VPIT.Misc,VIAWMisc);
     
  // Write Sequencer
     for ( i=1; i<StdSR ; i++ ) {
       outb(i,VIASR);
       outb(VPIT.SR[i-1],VIASR+1);
     }
  // Write CRTC
     fill_crtc_timing(crt_timing, vmode_index, video_bpp/8,IGA1);
    
  // Write Graphic Controller
     for ( i=0; i<StdGR ; i++ ) {
       outb(i,VIAGR);
       outb(VPIT.GR[i],VIAGR+1);
     }

  // Write Attribute Controller
     for ( i=0; i<StdAR ; i++ ) {
       inb(VIAStatus);
       outb(i,VIAAR);
       outb(VPIT.AR[i],VIAAR);
     }

     inb(VIAStatus);
     outb(0x20,VIAAR);

  /* Update Patch Register */
   
    if ((chip_info.gfx_chip_name == UNICHROME_CLE266) || (chip_info.gfx_chip_name == UNICHROME_K400))
    { 		    
        for( i=0; i< NUM_TOTAL_PATCH_MODE; i++ )
        {
            if (res_patch_table[i].mode_index==vmode_index)
            {
                for(j=0; j<res_patch_table[i].table_length; j++)
                {     
                   index = res_patch_table[i].io_reg_table[j].index;
                   port = res_patch_table[i].io_reg_table[j].port;
                   value = res_patch_table[i].io_reg_table[j].value;
                   mask = res_patch_table[i].io_reg_table[j].mask ; 
                   write_reg_mask(index, port, value, mask);
                }
            }
        }
   }
  
  /* Update Refresh Rate Setting */

  /* Clear On Screen */
  if (TV_ON)
  {
      tv_set_mode(vmode_index);
  } 
        
  if (DVI_ON)
  {
      dvi_set_mode(crt_timing, vmode_index, video_bpp, IGA1);
     
  } 
  
  if (LCD_ON)
  {
      lcd_set_mode(crt_timing, vmode_index, video_bpp, IGA1_IGA2);
  } 

  device_screen_on();
  
  return 1;
}

int get_pixclock(int hres, int vres, int vmode_refresh)
{
  int i;
  
  for(i=0; i<NUM_TOTAL_RES_MAP_REFRESH; i++)
  {
      if((hres==res_map_refresh_tbl[i].hres) && (vres==res_map_refresh_tbl[i].vres) && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
          return(res_map_refresh_tbl[i].pixclock);
  }
  return(RES_640X480_60HZ_PIXCLOCK); 		  
 	
}

int get_refresh(int hres, int vres, int pixclock)
{
  int i;
  for(i=0; i<NUM_TOTAL_RES_MAP_REFRESH; i++)
  {
      if((hres==res_map_refresh_tbl[i].hres) && (vres==res_map_refresh_tbl[i].vres) && (pixclock == res_map_refresh_tbl[i].pixclock))
          return(res_map_refresh_tbl[i].vmode_refresh);
  }
  return(60); 
}