hw.c

VIA Framebuffer driver

                    write_reg(SR44, VIASR, CLK/0x10000);
		    DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK/0x10000);
                    write_reg(SR45, VIASR, (CLK&0xFFFF)/0x100);
		    DEBUG_MSG(KERN_INFO "\nSR45=%x", (CLK&0xFFFF)/0x100);
                    write_reg(SR46, VIASR, CLK%0x100);
		    DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK%0x100);
                    break;
        }
        

    }
    
    if ((set_iga==IGA2) || (set_iga==IGA1_IGA2))
    {
        // Change D,N FOR LCK
	    switch(chip_info.gfx_chip_name) {    
                case UNICHROME_CLE266:
                case UNICHROME_K400:
                    write_reg(SR44, VIASR, CLK/0x100);        
                    write_reg(SR45, VIASR, CLK%0x100);        
                    break;
                case UNICHROME_K800:
                case UNICHROME_P880:
                    write_reg(SR4A, VIASR, CLK/0x10000);
                    write_reg(SR4B, VIASR, (CLK&0xFFFF)/0x100);
                    write_reg(SR4C, VIASR, CLK%0x100);
                break;
        }
        
    }

    // H.W. Reset : OFF
    write_reg_mask(CR17, VIACR, 0x80, BIT7);

    // Reset PLL
    if ((set_iga==IGA1) || (set_iga==IGA1_IGA2))
    {
        write_reg_mask(SR40, VIASR, 0x02, BIT1);
        write_reg_mask(SR40, VIASR, 0x00, BIT1);
    }
    
     if ((set_iga==IGA2) || (set_iga==IGA1_IGA2))
    {
        write_reg_mask(SR40, VIASR, 0x01, BIT0); 
        write_reg_mask(SR40, VIASR, 0x00, BIT0);
    }

    // Fire!
    RegTemp = inb(VIARMisc);
    outb(RegTemp | (BIT2+BIT3),VIAWMisc);
}

void load_crtc_timing(struct display_timing device_timing, int set_iga)
{
    int i;
    int load_reg_num=0;
    int reg_value=0;
    struct io_register *reg=NULL;
    
    for (i=0;i<12;i++)
    {
        if (set_iga == IGA1)
        {
	        switch(i) {
		        case H_TOTAL_INDEX:
		            reg_value = IGA1_HOR_TOTAL_FORMULA(device_timing.hor_total);
			        load_reg_num = iga1_crtc_reg.hor_total.reg_num;
			        reg = iga1_crtc_reg.hor_total.reg;
			        break;
		        case H_ADDR_INDEX:
		            reg_value = IGA1_HOR_ADDR_FORMULA(device_timing.hor_addr);
			        load_reg_num = iga1_crtc_reg.hor_addr.reg_num;
			        reg = iga1_crtc_reg.hor_addr.reg;
			        break;
		        case H_BLANK_SATRT_INDEX:
		            reg_value = IGA1_HOR_BLANK_START_FORMULA(device_timing.hor_blank_start);
			        load_reg_num = iga1_crtc_reg.hor_blank_start.reg_num;
			        reg = iga1_crtc_reg.hor_blank_start.reg;
			        break;
		        case H_BLANK_END_INDEX:
		            reg_value = IGA1_HOR_BLANK_END_FORMULA(device_timing.hor_blank_start, device_timing.hor_blank_end);
			        load_reg_num = iga1_crtc_reg.hor_blank_end.reg_num;
			        reg = iga1_crtc_reg.hor_blank_end.reg;
			        break;
		        case H_SYNC_SATRT_INDEX:
		            reg_value = IGA1_HOR_SYNC_START_FORMULA(device_timing.hor_sync_start);
			        load_reg_num = iga1_crtc_reg.hor_sync_start.reg_num;
			        reg = iga1_crtc_reg.hor_sync_start.reg;
			        break;
		        case H_SYNC_END_INDEX:
		            reg_value = IGA1_HOR_SYNC_END_FORMULA(device_timing.hor_sync_start, device_timing.hor_sync_end);
			        load_reg_num = iga1_crtc_reg.hor_sync_end.reg_num;
			        reg = iga1_crtc_reg.hor_sync_end.reg;
			        break;
		        case V_TOTAL_INDEX:
		            reg_value = IGA1_VER_TOTAL_FORMULA(device_timing.ver_total);
			        load_reg_num = iga1_crtc_reg.ver_total.reg_num;
			        reg = iga1_crtc_reg.ver_total.reg;
			        break;
		        case V_ADDR_INDEX:
		            reg_value = IGA1_VER_ADDR_FORMULA(device_timing.ver_addr);
			        load_reg_num = iga1_crtc_reg.ver_addr.reg_num;
			        reg = iga1_crtc_reg.ver_addr.reg;
			        break;
		        case V_BLANK_SATRT_INDEX:
		            reg_value = IGA1_VER_BLANK_START_FORMULA(device_timing.ver_blank_start);
			        load_reg_num = iga1_crtc_reg.ver_blank_start.reg_num;
			        reg = iga1_crtc_reg.ver_blank_start.reg;
			        break;
		        case V_BLANK_END_INDEX:
		            reg_value = IGA1_VER_BLANK_END_FORMULA(device_timing.ver_blank_start, device_timing.ver_blank_end);
			        load_reg_num = iga1_crtc_reg.ver_blank_end.reg_num;
			        reg = iga1_crtc_reg.ver_blank_end.reg;
			        break;
		        case V_SYNC_SATRT_INDEX:
		            reg_value = IGA1_VER_SYNC_START_FORMULA(device_timing.ver_sync_start);
			        load_reg_num = iga1_crtc_reg.ver_sync_start.reg_num;
			        reg = iga1_crtc_reg.ver_sync_start.reg;
			        break;
		        case V_SYNC_END_INDEX:
			        reg_value = IGA1_VER_SYNC_END_FORMULA(device_timing.ver_sync_start, device_timing.ver_sync_end);
			        load_reg_num = iga1_crtc_reg.ver_sync_end.reg_num;
			        reg = iga1_crtc_reg.ver_sync_end.reg;
			        break;

	        }
	    }
	    
	    if (set_iga == IGA1_IGA2)
	    {
	        switch(i) {
		        case H_TOTAL_INDEX:
		            reg_value = IGA1_HOR_TOTAL_FORMULA(device_timing.hor_total);
			        load_reg_num = iga1_shadow_crtc_reg.hor_total.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_total.reg;
			        break;
		        case H_ADDR_INDEX:
		            reg_value = IGA1_HOR_ADDR_FORMULA(device_timing.hor_addr);
			        load_reg_num = iga1_shadow_crtc_reg.hor_addr.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_addr.reg;
			        break;
		        case H_BLANK_SATRT_INDEX:
		            reg_value = IGA1_HOR_BLANK_START_FORMULA(device_timing.hor_blank_start);
			        load_reg_num = iga1_shadow_crtc_reg.hor_blank_start.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_blank_start.reg;
			        break;
		        case H_BLANK_END_INDEX:
		            reg_value = IGA1_HOR_BLANK_END_FORMULA(device_timing.hor_blank_start, device_timing.hor_blank_end);
			        load_reg_num = iga1_shadow_crtc_reg.hor_blank_end.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_blank_end.reg;
			        break;
		        case H_SYNC_SATRT_INDEX:
		            reg_value = IGA1_HOR_SYNC_START_FORMULA(device_timing.hor_sync_start);
			        load_reg_num = iga1_shadow_crtc_reg.hor_sync_start.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_sync_start.reg;
			        break;
		        case H_SYNC_END_INDEX:
		            reg_value = IGA1_HOR_SYNC_END_FORMULA(device_timing.hor_sync_start, device_timing.hor_sync_end);
			        load_reg_num = iga1_shadow_crtc_reg.hor_sync_end.reg_num;
			        reg = iga1_shadow_crtc_reg.hor_sync_end.reg;
			        break;
		        case V_TOTAL_INDEX:
		            reg_value = IGA1_VER_TOTAL_FORMULA(device_timing.ver_total);
			        load_reg_num = iga1_shadow_crtc_reg.ver_total.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_total.reg;
			        break;
		        case V_ADDR_INDEX:
		            reg_value = IGA1_VER_ADDR_FORMULA(device_timing.ver_addr);
			        load_reg_num = iga1_shadow_crtc_reg.ver_addr.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_addr.reg;
			        break;
		        case V_BLANK_SATRT_INDEX:
		            reg_value = IGA1_VER_BLANK_START_FORMULA(device_timing.ver_blank_start);
			        load_reg_num = iga1_shadow_crtc_reg.ver_blank_start.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_blank_start.reg;
			        break;
		        case V_BLANK_END_INDEX:
		            reg_value = IGA1_VER_BLANK_END_FORMULA(device_timing.ver_blank_start, device_timing.ver_blank_end);
			        load_reg_num = iga1_shadow_crtc_reg.ver_blank_end.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_blank_end.reg;
			        break;
		        case V_SYNC_SATRT_INDEX:
		            reg_value = IGA1_VER_SYNC_START_FORMULA(device_timing.ver_sync_start);
			        load_reg_num = iga1_shadow_crtc_reg.ver_sync_start.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_sync_start.reg;
			        break;
		        case V_SYNC_END_INDEX:
			        reg_value = IGA1_VER_SYNC_END_FORMULA(device_timing.ver_sync_start, device_timing.ver_sync_end);
			        load_reg_num = iga1_shadow_crtc_reg.ver_sync_end.reg_num;
			        reg = iga1_shadow_crtc_reg.ver_sync_end.reg;
			        break;

	        }       
	    }
	    
	    if (set_iga == IGA2)
	    {
	        switch(i) {
		        case H_TOTAL_INDEX:
		            reg_value = IGA2_HOR_TOTAL_FORMULA(device_timing.hor_total);
			        load_reg_num = iga2_crtc_reg.hor_total.reg_num;
			        reg = iga2_crtc_reg.hor_total.reg;
			        break;
		        case H_ADDR_INDEX:
		            reg_value = IGA2_HOR_ADDR_FORMULA(device_timing.hor_addr);
			        load_reg_num = iga2_crtc_reg.hor_addr.reg_num;
			        reg = iga2_crtc_reg.hor_addr.reg;
			        break;
		        case H_BLANK_SATRT_INDEX:
		            reg_value = IGA2_HOR_BLANK_START_FORMULA(device_timing.hor_blank_start);
			        load_reg_num = iga2_crtc_reg.hor_blank_start.reg_num;
			        reg = iga2_crtc_reg.hor_blank_start.reg;
			        break;
		        case H_BLANK_END_INDEX:
		            reg_value = IGA2_HOR_BLANK_END_FORMULA(device_timing.hor_blank_start, device_timing.hor_blank_end);
			        load_reg_num = iga2_crtc_reg.hor_blank_end.reg_num;
			        reg = iga2_crtc_reg.hor_blank_end.reg;
			        break;
		        case H_SYNC_SATRT_INDEX:
		            reg_value = IGA2_HOR_SYNC_START_FORMULA(device_timing.hor_sync_start);
			        load_reg_num = iga2_crtc_reg.hor_sync_start.reg_num;
			        reg = iga2_crtc_reg.hor_sync_start.reg;
			        break;
		        case H_SYNC_END_INDEX:
		            reg_value = IGA2_HOR_SYNC_END_FORMULA(device_timing.hor_sync_start, device_timing.hor_sync_end);
			        load_reg_num = iga2_crtc_reg.hor_sync_end.reg_num;
			        reg = iga2_crtc_reg.hor_sync_end.reg;
			        break;
		        case V_TOTAL_INDEX:
		            reg_value = IGA2_VER_TOTAL_FORMULA(device_timing.ver_total);
			        load_reg_num = iga2_crtc_reg.ver_total.reg_num;
			        reg = iga2_crtc_reg.ver_total.reg;
			        break;
		        case V_ADDR_INDEX:
		            reg_value = IGA2_VER_ADDR_FORMULA(device_timing.ver_addr);
			        load_reg_num = iga2_crtc_reg.ver_addr.reg_num;
			        reg = iga2_crtc_reg.ver_addr.reg;
			        break;
		        case V_BLANK_SATRT_INDEX:
		            reg_value = IGA2_VER_BLANK_START_FORMULA(device_timing.ver_blank_start);
			        load_reg_num = iga2_crtc_reg.ver_blank_start.reg_num;
			        reg = iga2_crtc_reg.ver_blank_start.reg;
			        break;
		        case V_BLANK_END_INDEX:
		            reg_value = IGA2_VER_BLANK_END_FORMULA(device_timing.ver_blank_start, device_timing.ver_blank_end);
			        load_reg_num = iga2_crtc_reg.ver_blank_end.reg_num;
			        reg = iga2_crtc_reg.ver_blank_end.reg;
			        break;
		        case V_SYNC_SATRT_INDEX:
		            reg_value = IGA2_VER_SYNC_START_FORMULA(device_timing.ver_sync_start);
			        load_reg_num = iga2_crtc_reg.ver_sync_start.reg_num;
			        reg = iga2_crtc_reg.ver_sync_start.reg;
			        break;
		        case V_SYNC_END_INDEX:
			        reg_value = IGA2_VER_SYNC_END_FORMULA(device_timing.ver_sync_start, device_timing.ver_sync_end);
			        load_reg_num = iga2_crtc_reg.ver_sync_end.reg_num;
			        reg = iga2_crtc_reg.ver_sync_end.reg;
			        break;

	        }
	     }
	     load_reg(reg_value, load_reg_num, reg, VIACR);
	}    
}
         
void fill_crtc_timing(struct crt_mode_table *crt_table, int mode_index, int bpp_byte, int set_iga)
{
    struct VideoModeTable *video_mode;
    struct display_timing crt_reg;
    int i;
    int index=0;
    int h_addr,v_addr;
    u32 pll_D_N;


    video_mode = &CLE266Modes[SearchModeSetting(mode_index)];
    
    for(i=0;i<video_mode->mode_array;i++)
    {
       index = i;

       if (crt_table[i].refresh_rate == crt_setting_info.refresh_rate)
       break;
    }
	
    crt_reg = crt_table[index].crtc;
    h_addr = crt_reg.hor_addr;
    v_addr = crt_reg.ver_addr;

   /* DEBUG_MSG(KERN_INFO "===Debug===");
    DEBUG_MSG(KERN_INFO "Index=%d\n", index);
    DEBUG_MSG(KERN_INFO "Refresh_rate=%d\n", crt_table[index].refresh_rate);
    DEBUG_MSG(KERN_INFO "HT=%d\n",crt_reg.hor_total);
    DEBUG_MSG(KERN_INFO "HAdr=%d\n",crt_reg.hor_addr);	
    DEBUG_MSG(KERN_INFO "HBS=%d\n",crt_reg.hor_blank_start);
    DEBUG_MSG(KERN_INFO "HBE=%d\n",crt_reg.hor_blank_end);	
    DEBUG_MSG(KERN_INFO "HSS=%d\n",crt_reg.hor_sync_start);
    DEBUG_MSG(KERN_INFO "HSE=%d\n",crt_reg.hor_sync_end);	

    DEBUG_MSG(KERN_INFO "VT=%d\n",crt_reg.ver_total);
    DEBUG_MSG(KERN_INFO "VAdr=%d\n",crt_reg.ver_addr);	
    DEBUG_MSG(KERN_INFO "VBS=%d\n",crt_reg.ver_blank_start);
    DEBUG_MSG(KERN_INFO "VBE=%d\n",crt_reg.ver_blank_end);	
    DEBUG_MSG(KERN_INFO "VSS=%d\n",crt_reg.ver_sync_start);
    DEBUG_MSG(KERN_INFO "VSE=%d\n",crt_reg.ver_sync_end);	*/
    
    if (set_iga == IGA1)
    {
        unlock_crt(); 	
        write_reg(CR09, VIACR, 0x00); //initial CR09=0 
        // update starting address
        write_reg(CR0C, VIACR, 0x00); //initial starting address
        write_reg(CR0D, VIACR, 0x00);
	    write_reg(CR34, VIACR, 0x00);
        write_reg_mask(CR48, VIACR, 0x00, BIT0+BIT1);
        write_reg_mask(CR11, VIACR, 0x00, BIT4+BIT5+BIT6);
        write_reg_mask(CR17, VIACR, 0x00, BIT7);
    }
    else
    {
        // update starting address
        write_reg(CR62, VIACR, 0x00); 
        write_reg(CR63, VIACR, 0x00);
        write_reg(CR64, VIACR, 0x00);
    }
    
    switch(set_iga) {
        case IGA1:
            load_crtc_timing(crt_reg, IGA1);
            break;
        case IGA2:
            load_crtc_timing(crt_reg, IGA2);
            break;
        case IGA1_IGA2:
            load_crtc_timing(crt_reg, IGA1_IGA2); 
            load_crtc_timing(crt_reg, IGA2);       
            break;
    }    
        
    load_fix_bit_crtc_reg();