hw.c

VIA Framebuffer driver

                write_reg_mask(CR99, VIACR, 0x00, BIT4);
            else
                write_reg_mask(CR99, VIACR, 0x10, BIT4);    
            write_reg_mask(CR6A, VIACR, 0x01, BIT0);    
            break;
        case INTERFACE_DFP:
            if (set_iga== IGA1)
            {
                write_reg_mask(CR97, VIACR, 0x00, BIT4);
                write_reg_mask(CR99, VIACR, 0x00, BIT4);
            }
            else
            {
                write_reg_mask(CR97, VIACR, 0x10, BIT4);
                write_reg_mask(CR99, VIACR, 0x10, BIT4);    
            }
            write_reg_mask(CR6A, VIACR, 0x01, BIT0);
            break;               
    } 
}

/* Search Mode Index */
static int SearchModeSetting( int ModeInfoIndex )
{
   int i=0;

   while ( ( i<NUM_TOTAL_MODETABLE ) && ( ModeInfoIndex != CLE266Modes[i].ModeIndex) ){i++;}
   if( ( i >= NUM_TOTAL_MODETABLE ) ) i=0;
   return i;

}

void load_fix_bit_crtc_reg(void)
{
     write_reg_mask(CR03, VIACR, 0x80, BIT7);   // always set to 1
     write_reg(CR18, VIACR, 0xff);                              // line compare should set all bits = 1 (extend modes)
     write_reg_mask(CR07, VIACR, 0x10, BIT4);                   // line compare should set all bits = 1 (extend modes)
     write_reg_mask(CR09, VIACR, 0x40, BIT6);                   // line compare should set all bits = 1 (extend modes)
     write_reg_mask(CR35, VIACR, 0x10, BIT4);                   // line compare should set all bits = 1 (extend modes)
     write_reg_mask(CR33, VIACR, 0x05, BIT0+BIT1+BIT2);    	// line compare should set all bits = 1 (extend modes)
     //write_reg_mask(CR32, VIACR, 0x01, BIT0);
     write_reg(CR17, VIACR, 0xe3);                              // extend mode always set to e3h
     write_reg(CR08, VIACR, 0x00);                              // extend mode always set to 0h
     write_reg(CR14, VIACR, 0x00);                              // extend mode always set to 0h
     
     if ((chip_info.gfx_chip_name == UNICHROME_CLE266) && (chip_info.gfx_chip_revision == CLE266_REVISION_AX))
         write_reg_mask(SR1A, VIASR, 0x02, BIT1);
    
}

void load_reg(int timing_value, int load_reg_num, struct io_register *reg, int io_type)
{
    int reg_mask;
    int bit_num=0;
    int data;
    int i,j;
    int shift_next_reg;
    int start_index, end_index, cr_index;
    u16 get_bit;



    for (i=0; i<load_reg_num; i++)
    {
	    reg_mask = 0;
	    data=0;
	    start_index = reg[i].start_bit;
	    end_index = reg[i].end_bit;
	    cr_index = reg[i].io_addr;

	    shift_next_reg = bit_num;
	    for(j=start_index;j<=end_index;j++)
	    {
		    //if (bit_num==8) timing_value = timing_value >>8;
		    reg_mask = reg_mask | (BIT0 << j);
		    get_bit = (timing_value & (BIT0 << bit_num));
		    data = data | ((get_bit >> shift_next_reg)<< start_index);
		    bit_num ++;
	    }
	    if (io_type == VIACR)
	    {
		    //DEBUG_MSG(KERN_INFO "i=%2d %2d %2d %2d\n", i, cr_index, data, reg_mask);    
	        write_reg_mask(cr_index, VIACR, data, reg_mask);
		
	    }
	    else
	    {
		    //DEBUG_MSG(KERN_INFO "\nSR = %2d", cr_index);    
		    //DEBUG_MSG(KERN_INFO "\ni=%2d %2d %2d %2d", i, cr_index, data, reg_mask);    
	        write_reg_mask(cr_index, VIASR, data, reg_mask);
	    }    

    }

}

/* Write Registers */
static void WriteRegX(struct io_reg RegTable[],int ItemNum)
{
   int               i;
   unsigned char     RegTemp;

   //DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum );


   for( i=0; i< ItemNum; i++ ){
       outb( RegTable[i].index, RegTable[i].port );
       RegTemp = inb(RegTable[i].port+1 );
       RegTemp = ( RegTemp & ( ~RegTable[i].mask ) ) | RegTable[i].value ;
       outb( RegTemp, RegTable[i].port+1 );
   }
}

void load_offset_reg(int h_addr, int bpp_byte, int set_iga)
{
    int reg_value;
    int load_reg_num;
    struct io_register *reg;
    
    
    switch(set_iga) {
        case IGA1_IGA2:
        case IGA1:
            reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
            load_reg_num = offset_reg.iga1_offset_reg.reg_num;
            reg = offset_reg.iga1_offset_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIACR);
            if (set_iga == IGA1)
                break;
        case IGA2:
            reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
            load_reg_num = offset_reg.iga2_offset_reg.reg_num;
            reg = offset_reg.iga2_offset_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIACR);    
            break;
    }
}  

void load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
{
    int reg_value;
    int load_reg_num;
    struct io_register *reg=NULL;
    
    switch(set_iga) {
        case IGA1_IGA2:
        case IGA1:    
            reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
            load_reg_num = fetch_count_reg.iga1_fetch_count_reg.reg_num;
            reg = fetch_count_reg.iga1_fetch_count_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIASR);
            if (set_iga == IGA1)            
                break;
        case IGA2:
            reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
            load_reg_num = fetch_count_reg.iga2_fetch_count_reg.reg_num;
            reg = fetch_count_reg.iga2_fetch_count_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIACR);
            break;
    }

}


void load_FIFO_reg(int set_iga, int hor_active, int ver_active)
{
    int reg_value;
    int load_reg_num;
    struct io_register *reg=NULL;
    int iga1_fifo_max_depth=0, iga1_fifo_threshold=0, iga1_gfx_preg_threshold=0, iga1_display_gueue_expire_num=0;
    int iga2_fifo_max_depth=0, iga2_fifo_threshold=0, iga2_gfx_preg_threshold=0, iga2_display_gueue_expire_num=0;
    
    
    if (set_iga == IGA1)
    {
        if (chip_info.gfx_chip_name == UNICHROME_K800)
        {
            iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
            iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
            iga1_gfx_preg_threshold = K800_IGA1_GFX_PREQ_THRESHOLD;
            // If resolution > 1280x1024, expire length = 64, else  expire length = 128
            if ((hor_active > 1280) && (ver_active > 1024))
                iga1_display_gueue_expire_num = 16;
            else
                iga1_display_gueue_expire_num = K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
            
        }
        
        if (chip_info.gfx_chip_name == UNICHROME_P880)
        {
            iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
            iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
            iga1_gfx_preg_threshold = P880_IGA1_GFX_PREQ_THRESHOLD;
            iga1_display_gueue_expire_num = P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
            
            // If resolution > 1280x1024, expire length = 64, else  expire length = 128
            if ((hor_active > 1280) && (ver_active > 1024))
                iga1_display_gueue_expire_num = 16;
            else
                iga1_display_gueue_expire_num = P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
        }
                        
        // Set Display FIFO Depath Select
        reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
        load_reg_num = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
        reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIASR);
        
        // Set Display FIFO Threshold Select
        reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
        load_reg_num = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num;
        reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg;
	    //DEBUG_MSG(KERN_INFO "\n Display FIFO Threhold Select Value=%2d REG_NUM=%2d",reg_value,load_reg_num); 
        load_reg(reg_value, load_reg_num, reg, VIASR);  
        
        // Set GFX PREG Threshold Select
        reg_value = iga1_gfx_preg_threshold;
        load_reg_num = gfx_preq_thresold_select_reg.iga1_gfx_preq_thresold_select_reg.reg_num;
        reg = gfx_preq_thresold_select_reg.iga1_gfx_preq_thresold_select_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIASR);
        
        // Set Display Gueue Expire Num
        reg_value = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_gueue_expire_num);
        load_reg_num = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num;
        reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIASR);
         
    }
    else
    {
        if (chip_info.gfx_chip_name == UNICHROME_K800)
        {
            iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
            iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
            iga2_gfx_preg_threshold = K800_IGA2_GFX_PREQ_THRESHOLD;
            
            // If resolution > 1280x1024, expire length = 64, else  expire length = 128
            if ((hor_active > 1280) && (ver_active > 1024))
                iga2_display_gueue_expire_num = 16;
            else
                iga2_display_gueue_expire_num = K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
        }
        
        if (chip_info.gfx_chip_name == UNICHROME_P880)
        {
            iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
            iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
            iga2_gfx_preg_threshold = P880_IGA2_GFX_PREQ_THRESHOLD;
                        
            // If resolution > 1280x1024, expire length = 64, else  expire length = 128
            if ((hor_active > 1280) && (ver_active > 1024))
                iga2_display_gueue_expire_num = 16;
            else
                iga2_display_gueue_expire_num = P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
        }
        
        if (chip_info.gfx_chip_name == UNICHROME_K800)
        {
            // Set Display FIFO Depath Select
            reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)-1; // Patch LCD in IGA2 case 
            load_reg_num = display_fifo_depth_reg.iga2_fifo_depth_select_reg.reg_num;
            reg = display_fifo_depth_reg.iga2_fifo_depth_select_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIACR);
        }
        else
        {
        
            // Set Display FIFO Depath Select
            reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
            load_reg_num = display_fifo_depth_reg.iga2_fifo_depth_select_reg.reg_num;
            reg = display_fifo_depth_reg.iga2_fifo_depth_select_reg.reg;
            load_reg(reg_value, load_reg_num, reg, VIACR);
        }    
        
        // Set Display FIFO Threshold Select
        reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
        load_reg_num = fifo_threshold_select_reg.iga2_fifo_threshold_select_reg.reg_num;
        reg = fifo_threshold_select_reg.iga2_fifo_threshold_select_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIACR);  
        
        // Set GFX PREG Threshold Select
        reg_value = iga2_gfx_preg_threshold;
        load_reg_num = gfx_preq_thresold_select_reg.iga2_gfx_preq_thresold_select_reg.reg_num;
        reg = gfx_preq_thresold_select_reg.iga2_gfx_preq_thresold_select_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIACR);
        
        // Set Display Gueue Expire Num
        reg_value = IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga2_display_gueue_expire_num);
        load_reg_num = display_queue_expire_num_reg.iga2_display_queue_expire_num_reg.reg_num;
        reg = display_queue_expire_num_reg.iga2_display_queue_expire_num_reg.reg;
        load_reg(reg_value, load_reg_num, reg, VIACR);
      
    }
    
}

u32 get_clk_value(int clk)
{
   int i;
   
   for(i=0; i<NUM_TOTAL_PLL_TABLE; i++)
   {
        if(clk==pll_value[i].clk)
        {
            switch(chip_info.gfx_chip_name) {    
                case UNICHROME_CLE266:
                case UNICHROME_K400:
                    return(pll_value[i].cle266_pll);    
                break;
                case UNICHROME_K800:
                case UNICHROME_P880:
                    return(pll_value[i].k800_pll);
                break;
             }
        }        
    }            
   DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");    
   return(0);
}

// Set VCLK
void SetVCLK( u32 CLK, int set_iga )
{
    unsigned char RegTemp;

    // H.W. Reset : ON
    write_reg_mask(CR17, VIACR, 0x00, BIT7);

    if ((set_iga==IGA1) || (set_iga==IGA1_IGA2))
    {  

        // Change D,N FOR VCLK
	    switch(chip_info.gfx_chip_name) {    
                case UNICHROME_CLE266:
                case UNICHROME_K400:
                    write_reg(SR46, VIASR, CLK/0x100);        
                    write_reg(SR47, VIASR, CLK%0x100);        
                    break;
                case UNICHROME_K800:
                case UNICHROME_P880: