hw.h

VIA Framebuffer driver

struct iga1_shadow_ver_blank_start {
    int     reg_num;
    struct  io_register reg[IGA1_SHADOW_VER_BLANK_START_REG_NUM];
};

/* IGA1 Shadow Vertical Blank End */
struct iga1_shadow_ver_blank_end {
    int     reg_num;
    struct  io_register reg[IGA1_SHADOW_VER_BLANK_END_REG_NUM];
};

/* IGA1 Shadow Vertical Sync Start */
struct iga1_shadow_ver_sync_start {
    int     reg_num;
    struct  io_register reg[IGA1_SHADOW_VER_SYNC_START_REG_NUM];
};

/* IGA1 Shadow Vertical Sync End */
struct iga1_shadow_ver_sync_end {
    int     reg_num;
    struct  io_register reg[IGA1_SHADOW_VER_SYNC_END_REG_NUM];
};

//************************************************//
//      Define IGA2 Display Timing                //
//************************************************//

/* IGA2 Horizontal Total */
struct iga2_hor_total {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_TOTAL_REG_NUM];
};

/* IGA2 Horizontal Addressable Video */
struct iga2_hor_addr {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_ADDR_REG_NUM];
};

/* IGA2 Horizontal Blank Start */
struct iga2_hor_blank_start {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
};

/* IGA2 Horizontal Blank End */
struct iga2_hor_blank_end {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
};

/* IGA2 Horizontal Sync Start */
struct iga2_hor_sync_start {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
};

/* IGA2 Horizontal Sync End */
struct iga2_hor_sync_end {
    int     reg_num;
    struct  io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
};

/* IGA2 Vertical Total */
struct iga2_ver_total {
    int     reg_num;
    struct  io_register reg[IGA2_VER_TOTAL_REG_NUM];
};

/* IGA2 Vertical Addressable Video */
struct iga2_ver_addr {
    int     reg_num;
    struct  io_register reg[IGA2_VER_ADDR_REG_NUM];
};

/* IGA2 Vertical Blank Start */
struct iga2_ver_blank_start {
    int     reg_num;
    struct  io_register reg[IGA2_VER_BLANK_START_REG_NUM];
};

/* IGA2 Vertical Blank End */
struct iga2_ver_blank_end {
    int     reg_num;
    struct  io_register reg[IGA2_VER_BLANK_END_REG_NUM];
};

/* IGA2 Vertical Sync Start */
struct iga2_ver_sync_start {
    int     reg_num;
    struct  io_register reg[IGA2_VER_SYNC_START_REG_NUM];
};

/* IGA2 Vertical Sync End */
struct iga2_ver_sync_end {
    int     reg_num;
    struct  io_register reg[IGA2_VER_SYNC_END_REG_NUM];
};

/* IGA1 Offset Register */
struct iga1_offset {
    int     reg_num;
    struct  io_register reg[IGA1_OFFSET_REG_NUM];
}; 

/* IGA2 Offset Register */
struct iga2_offset {
    int     reg_num;
    struct  io_register reg[IGA2_OFFSET_REG_NUM];
}; 

struct offset{
    struct iga1_offset            iga1_offset_reg;
    struct iga2_offset            iga2_offset_reg;
};

/* IGA1 Fetch Count Register */
struct iga1_fetch_count {
    int     reg_num;
    struct  io_register reg[IGA1_FETCH_COUNT_REG_NUM];
}; 

/* IGA2 Fetch Count Register */
struct iga2_fetch_count {
    int     reg_num;
    struct  io_register reg[IGA2_FETCH_COUNT_REG_NUM];
}; 

struct fetch_count{
    struct iga1_fetch_count       iga1_fetch_count_reg;
    struct iga2_fetch_count       iga2_fetch_count_reg;
};

/* Starting Address Register */
struct iga1_starting_addr {
    int     reg_num;
    struct  io_register reg[IGA1_STARTING_ADDR_REG_NUM];
}; 

struct iga2_starting_addr {
    int     reg_num;
    struct  io_register reg[IGA2_STARTING_ADDR_REG_NUM];
}; 

struct starting_addr {
    struct iga1_starting_addr       iga1_starting_addr_reg;
    struct iga2_starting_addr       iga2_starting_addr_reg;
};

/* LCD Power Sequence Timer */
struct lcd_pwd_seq_td0{
    int     reg_num;
    struct  io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
};

struct lcd_pwd_seq_td1{
    int     reg_num;
    struct  io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
};

struct lcd_pwd_seq_td2{
    int     reg_num;
    struct  io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
};

struct lcd_pwd_seq_td3{
    int     reg_num;
    struct  io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
};

struct _lcd_pwd_seq_timer{
    struct lcd_pwd_seq_td0       td0;
    struct lcd_pwd_seq_td1       td1;
    struct lcd_pwd_seq_td2       td2;
    struct lcd_pwd_seq_td3       td3;
};

/* LCD Scaling Factor */
struct _lcd_hor_scaling_factor{
    int     reg_num;
    struct  io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
};

struct _lcd_ver_scaling_factor{
    int     reg_num;
    struct  io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
};


struct _lcd_scaling_factor{
    struct _lcd_hor_scaling_factor  lcd_hor_scaling_factor;
    struct _lcd_ver_scaling_factor  lcd_ver_scaling_factor;
};

struct pll_map {
    u32     clk;
    u32     cle266_pll;
    u32     k800_pll;
}; 

struct rgbLUT {
    u8     red;
    u8     green;
    u8     blue;
};

struct lcd_pwd_seq_timer {
    u16     td0;
    u16     td1;
    u16     td2;
    u16     td3;    
};


// Display FIFO Relation Registers
struct iga1_fifo_depth_select {
    int     reg_num;
    struct  io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
};

struct iga1_fifo_threshold_select {
    int     reg_num;
    struct  io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];    
};

struct iga1_gfx_preq_thresold_select {
    int     reg_num;
    struct  io_register reg[IGA1_GFX_PREQ_THRESHOLD_REG_NUM];    
};

struct iga1_display_queue_expire_num {
    int     reg_num;
    struct  io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];    
};

struct iga2_fifo_depth_select {
    int     reg_num;
    struct  io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
};

struct iga2_fifo_threshold_select {
    int     reg_num;
    struct  io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
};

struct iga2_gfx_preq_thresold_select {
    int     reg_num;
    struct  io_register reg[IGA2_GFX_PREQ_THRESHOLD_REG_NUM];
};

struct iga2_display_queue_expire_num {
    int     reg_num;
    struct  io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];    
};

struct fifo_depth_select {
    struct  iga1_fifo_depth_select iga1_fifo_depth_select_reg;
    struct  iga2_fifo_depth_select iga2_fifo_depth_select_reg;
};

struct fifo_threshold_select {
    struct  iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
    struct  iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
};

struct gfx_preq_thresold_select {
    struct  iga1_gfx_preq_thresold_select iga1_gfx_preq_thresold_select_reg;
    struct  iga2_gfx_preq_thresold_select iga2_gfx_preq_thresold_select_reg;
};

struct display_queue_expire_num {
    struct  iga1_display_queue_expire_num iga1_display_queue_expire_num_reg;
    struct  iga2_display_queue_expire_num iga2_display_queue_expire_num_reg;
};

 

struct iga1_crtc_timing {
    struct iga1_hor_total         hor_total;
    struct iga1_hor_addr          hor_addr;
    struct iga1_hor_blank_start   hor_blank_start;
    struct iga1_hor_blank_end     hor_blank_end;
    struct iga1_hor_sync_start    hor_sync_start;
    struct iga1_hor_sync_end      hor_sync_end;
    struct iga1_ver_total         ver_total;
    struct iga1_ver_addr          ver_addr;
    struct iga1_ver_blank_start   ver_blank_start;
    struct iga1_ver_blank_end     ver_blank_end;
    struct iga1_ver_sync_start    ver_sync_start;
    struct iga1_ver_sync_end      ver_sync_end;
};

struct iga1_shadow_crtc_timing {
    struct iga1_shadow_hor_total        hor_total;
    struct iga1_hor_addr                hor_addr;
    struct iga1_hor_blank_start         hor_blank_start;
    struct iga1_shadow_hor_blank_end    hor_blank_end;
    struct iga1_hor_sync_start          hor_sync_start;
    struct iga1_hor_sync_end            hor_sync_end;
    struct iga1_shadow_ver_total        ver_total;
    struct iga1_shadow_ver_addr         ver_addr;
    struct iga1_shadow_ver_blank_start  ver_blank_start;
    struct iga1_shadow_ver_blank_end    ver_blank_end;
    struct iga1_shadow_ver_sync_start   ver_sync_start;
    struct iga1_shadow_ver_sync_end     ver_sync_end;
};

struct iga2_crtc_timing {
    struct iga2_hor_total         hor_total;
    struct iga2_hor_addr          hor_addr;
    struct iga2_hor_blank_start   hor_blank_start;
    struct iga2_hor_blank_end     hor_blank_end;
    struct iga2_hor_sync_start    hor_sync_start;
    struct iga2_hor_sync_end      hor_sync_end;
    struct iga2_ver_total         ver_total;
    struct iga2_ver_addr          ver_addr;
    struct iga2_ver_blank_start   ver_blank_start;
    struct iga2_ver_blank_end     ver_blank_end;
    struct iga2_ver_sync_start    ver_sync_start;
    struct iga2_ver_sync_end      ver_sync_end;
};


static struct pll_map pll_value[] = {
    {CLK_25_175M,  CLE266_PLL_25_175M,  K800_PLL_25_175M},
    {CLK_26_880M,  CLE266_PLL_26_880M,  K800_PLL_26_880M},