📄 at91sam9rl.h
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AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register} AT91S_DBGU, *AT91PS_DBGU;// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG// *****************************************************************************// SOFTWARE API DEFINITION FOR Parallel Input Output Controler// *****************************************************************************typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register} AT91S_PIO, *AT91PS_PIO;// *****************************************************************************// SOFTWARE API DEFINITION FOR Power Management Controler// *****************************************************************************typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG PMC_UCKR; // UTMI Clock Configuration Register AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG PMC_PLLAR; // PLL A Register AT91_REG PMC_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved1[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register} AT91S_PMC, *AT91PS_PMC;// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock#define AT91C_PMC_OTG ((unsigned int) 0x1 << 5) // (PMC) USB OTG Clock#define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- #define AT91C_CKGR_UPLLEN ((unsigned int) 0x1 << 16) // (PMC) UTMI PLL Enable#define AT91C_CKGR_UPLLEN_DISABLED ((unsigned int) 0x0 << 16) // (PMC) The UTMI PLL is disabled#define AT91C_CKGR_UPLLEN_ENABLED ((unsigned int) 0x1 << 16) // (PMC) The UTMI PLL is enabled#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0xF << 20) // (PMC) UTMI Oscillator Start-up Time#define AT91C_CKGR_BIASEN ((unsigned int) 0x1 << 24) // (PMC) UTMI BIAS Enable#define AT91C_CKGR_BIASEN_DISABLED ((unsigned int) 0x0 << 24) // (PMC) The UTMI BIAS is disabled#define AT91C_CKGR_BIASEN_ENABLED ((unsigned int) 0x1 << 24) // (PMC) The UTMI BIAS is enabled#define AT91C_CKGR_BIASCOUNT ((unsigned int) 0xF << 28) // (PMC) UTMI BIAS Start-up Time// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (PMC) Main Oscillator Enable#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (PMC) Main Oscillator Bypass#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (PMC) Main Oscillator Start-up Time// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (PMC) Main Clock Frequency#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (PMC) Main Clock Ready// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- #define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (PMC) Divider A Selected#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (PMC) Divider A output is 0#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (PMC) Divider A is bypassed#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (PMC) PLL A Counter#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (PMC) PLL A Output Frequency Range#define AT91C_CKGR_OUTA_0 ⌨️ 快捷键说明
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