📄 at91sam9rl.h
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#define AT91C_SMC_NWAITM ((unsigned int) 0x3 << 5) // (SMC) NWAIT Mode#define AT91C_SMC_NWAITM_NWAIT_DISABLE ((unsigned int) 0x0 << 5) // (SMC) External NWAIT disabled.#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN ((unsigned int) 0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY ((unsigned int) 0x3 << 5) // (SMC) External NWAIT enabled in ready mode.#define AT91C_SMC_BAT ((unsigned int) 0x1 << 8) // (SMC) Byte Access Type#define AT91C_SMC_BAT_BYTE_SELECT ((unsigned int) 0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.#define AT91C_SMC_BAT_BYTE_WRITE ((unsigned int) 0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.#define AT91C_SMC_DBW ((unsigned int) 0x3 << 12) // (SMC) Data Bus Width#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS ((unsigned int) 0x0 << 12) // (SMC) 8 bits.#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS ((unsigned int) 0x1 << 12) // (SMC) 16 bits.#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS ((unsigned int) 0x2 << 12) // (SMC) 32 bits.#define AT91C_SMC_TDF ((unsigned int) 0xF << 16) // (SMC) Data Float Time.#define AT91C_SMC_TDFEN ((unsigned int) 0x1 << 20) // (SMC) TDF Enabled.#define AT91C_SMC_PMEN ((unsigned int) 0x1 << 24) // (SMC) Page Mode Enabled.#define AT91C_SMC_PS ((unsigned int) 0x3 << 28) // (SMC) Page Size#define AT91C_SMC_PS_SIZE_FOUR_BYTES ((unsigned int) 0x0 << 28) // (SMC) 4 bytes.#define AT91C_SMC_PS_SIZE_EIGHT_BYTES ((unsigned int) 0x1 << 28) // (SMC) 8 bytes.#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES ((unsigned int) 0x2 << 28) // (SMC) 16 bytes.#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES ((unsigned int) 0x3 << 28) // (SMC) 32 bytes.// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- // *****************************************************************************// SOFTWARE API DEFINITION FOR AHB Matrix Interface// *****************************************************************************typedef struct _AT91S_MATRIX { AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 : rom AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 ; htcm AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 : lcdc AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 : usb_dev_hs AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 : ebi AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 : bridge AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 AT91_REG MATRIX_MCFG8; // Master Configuration Register 8 AT91_REG Reserved0[7]; // AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 : rom AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 : htcm AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 : lcdc AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 : usb_dev_hs AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 ; ebi AT91_REG MATRIX_SCFG5; // Slave Configuration Register 5 : bridge AT91_REG MATRIX_SCFG6; // Slave Configuration Register 6 AT91_REG MATRIX_SCFG7; // Slave Configuration Register 7 AT91_REG Reserved1[8]; // AT91_REG MATRIX_PRAS0; // PRAS0 : rom AT91_REG MATRIX_PRBS0; // PRBS0 : rom AT91_REG MATRIX_PRAS1; // PRAS1 : htcm AT91_REG MATRIX_PRBS1; // PRBS1 : htcm AT91_REG MATRIX_PRAS2; // PRAS2 : lcdc AT91_REG MATRIX_PRBS2; // PRBS2 : lcdc AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs AT91_REG MATRIX_PRAS4; // PRAS4 : ebi AT91_REG MATRIX_PRBS4; // PRBS4 : ebi AT91_REG MATRIX_PRAS5; // PRAS5 : bridge AT91_REG MATRIX_PRBS5; // PRBS5 : bridge AT91_REG MATRIX_PRAS6; // PRAS6 AT91_REG MATRIX_PRBS6; // PRBS6 AT91_REG MATRIX_PRAS7; // PRAS7 AT91_REG MATRIX_PRBS7; // PRBS7 AT91_REG Reserved2[16]; // AT91_REG MATRIX_MRCR; // Master Remp Control Register } AT91S_MATRIX, *AT91PS_MATRIX;// -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom -------- #define AT91C_MATRIX_ULBT ((unsigned int) 0x7 << 0) // (MATRIX) Undefined Length Burst Type// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm -------- // -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm -------- // -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs -------- // -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 -------- // -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 -------- // -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge -------- // -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps -------- // -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps -------- // -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- #define AT91C_MATRIX_SLOT_CYCLE ((unsigned int) 0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst#define AT91C_MATRIX_DEFMSTR_TYPE ((unsigned int) 0x3 << 16) // (MATRIX) Default Master Type#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR ((unsigned int) 0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR ((unsigned int) 0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR ((unsigned int) 0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.#define AT91C_MATRIX_FIXED_DEFMSTR0 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC ((unsigned int) 0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC ((unsigned int) 0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI ((unsigned int) 0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC ((unsigned int) 0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_USB ((unsigned int) 0x8 << 18) // (MATRIX) USB Master is Default Master#define AT91C_MATRIX_ARBT ((unsigned int) 0x3 << 24) // (MATRIX) Arbitration Type// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- #define AT91C_MATRIX_FIXED_DEFMSTR1 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC ((unsigned int) 0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC ((unsigned int) 0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI ((unsigned int) 0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC ((unsigned int) 0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_USB ((unsigned int) 0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- #define AT91C_MATRIX_FIXED_DEFMSTR2 ((unsigned int) 0x1 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- #define AT91C_MATRIX_FIXED_DEFMSTR3 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC ((unsigned int) 0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC ((unsigned int) 0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI ((unsigned int) 0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_EMAC ((unsigned int) 0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_USB ((unsigned int) 0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- #define AT91C_MATRIX_FIXED_DEFMSTR4 ((unsigned int) 0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master// -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 -------- #define AT91C_MATRIX_FIXED_DEFMSTR5 ((unsigned int) 0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_PDC ((unsigned int) 0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_2DGC ((unsigned int) 0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ISI ((unsigned int) 0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_DMA ((unsigned int) 0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_EMAC ((unsigned int) 0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_USB ((unsigned int) 0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 -------- #define AT91C_MATRIX_FIXED_DEFMSTR6 ((unsigned int) 0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master⌨️ 快捷键说明
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