at91sam9rl.h

试用于arm9 at91sram9260开发板的uboot程序

//  ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
//  ----------------------------------------------------------------------------
//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//  ----------------------------------------------------------------------------
// File Name           : AT91SAM9RL64.h
// Object              : AT91SAM9RL64 definitions
// Generated           : AT91 SW Application Group  11/13/2006 (17:21:41)
// 
// CVS Reference       : /AT91SAM9RL64.pl/1.19/Mon Nov 13 16:21:11 2006//
// CVS Reference       : /SYS_SAM9RL64.pl/1.2/Mon Nov 13 16:23:12 2006//
// CVS Reference       : /HMATRIX1_SAM9RL64.pl/1.1/Wed Sep 13 15:29:30 2006//
// CVS Reference       : /CCR_SAM9RL64.pl/1.1/Wed Sep 13 15:29:30 2006//
// CVS Reference       : /PMC_CAP9.pl/1.2/Thu Oct 26 11:26:44 2006//
// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 11:12:14 2005//
// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug 09 09:52:25 2004//
// CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 08:16:23 2004//
// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb 09 16:16:57 2005//
// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 16:04:01 2004//
// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb 03 08:02:11 2005//
// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 12:54:41 2005//
// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb 03 09:29:42 2005//
// CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov 04 12:57:00 2004//
// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct 06 13:16:58 2004//
// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov 04 12:57:22 2004//
// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov 04 12:56:22 2004//
// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov 04 12:58:52 2004//
// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar 09 15:31:51 2005//
// CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun 03 12:20:23 2005//
// CVS Reference       : /TWI_6061B.pl/1.2/Tue Sep 12 12:35:28 2006//
// CVS Reference       : /US_6089J.pl/1.2/Wed Oct 11 12:26:02 2006//
// CVS Reference       : /SSC_6078B.pl/1.1/Wed Jul 13 14:25:46 2005//
// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 13:23:02 2005//
// CVS Reference       : /AC97C_XXXX.pl/1.3/Tue Feb 22 16:08:27 2005//
// CVS Reference       : /PWM_6044D.pl/1.2/Tue May 10 11:39:09 2005//
// CVS Reference       : /LCDC_6063A.pl/1.3/Fri Dec 09 09:59:26 2005//
// CVS Reference       : /HDMA_SAM9RL64.pl/1.2/Wed Sep 06 15:25:21 2006//
// CVS Reference       : /UDPHS_SAM9265.pl/1.8/Tue Sep 12 12:35:29 2006//
// CVS Reference       : /TSC_XXXX.pl/1.1/Wed Oct 11 13:03:27 2006//
// CVS Reference       : /RTC_1245D.pl/1.3/Fri Sep 17 13:01:31 2004//
//  ----------------------------------------------------------------------------

#ifndef AT91SAM9RL64_H
#define AT91SAM9RL64_H

typedef volatile unsigned int AT91_REG;// Hardware register definition

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYS {
	AT91_REG	 Reserved0[3904]; 	// 
	AT91_REG	 SYS_RSTC_RCR; 	// Reset Control Register
	AT91_REG	 SYS_RSTC_RSR; 	// Reset Status Register
	AT91_REG	 SYS_RSTC_RMR; 	// Reset Mode Register
	AT91_REG	 Reserved1[1]; 	// 
	AT91_REG	 SYS_SHDWC_SHCR; 	// Shut Down Control Register
	AT91_REG	 SYS_SHDWC_SHMR; 	// Shut Down Mode Register
	AT91_REG	 SYS_SHDWC_SHSR; 	// Shut Down Status Register
	AT91_REG	 Reserved2[1]; 	// 
	AT91_REG	 SYS_RTTC0_RTMR; 	// Real-time Mode Register
	AT91_REG	 SYS_RTTC0_RTAR; 	// Real-time Alarm Register
	AT91_REG	 SYS_RTTC0_RTVR; 	// Real-time Value Register
	AT91_REG	 SYS_RTTC0_RTSR; 	// Real-time Status Register
	AT91_REG	 SYS_PITC_PIMR; 	// Period Interval Mode Register
	AT91_REG	 SYS_PITC_PISR; 	// Period Interval Status Register
	AT91_REG	 SYS_PITC_PIVR; 	// Period Interval Value Register
	AT91_REG	 SYS_PITC_PIIR; 	// Period Interval Image Register
	AT91_REG	 SYS_WDTC_WDCR; 	// Watchdog Control Register
	AT91_REG	 SYS_WDTC_WDMR; 	// Watchdog Mode Register
	AT91_REG	 SYS_WDTC_WDSR; 	// Watchdog Status Register
	AT91_REG	 Reserved3[1]; 	// 
	AT91_REG	 SYS_GPBR[4]; 	// General Purpose Register
	AT91_REG	 SYS_SLCKSEL; 	// Slow Clock Selection Register
} AT91S_SYS, *AT91PS_SYS;

// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- 
#define AT91C_GPBR_GPRV       ((unsigned int) 0x0 <<  0) // (SYS) General Purpose Register Value
// -------- SLCKSEL : (SYS Offset: 0x3d60) Slow Clock Selection Register -------- 
#define AT91C_SLCKSEL_RCEN    ((unsigned int) 0x1 <<  0) // (SYS) Enable Internal RC Oscillator
#define AT91C_SLCKSEL_OSC32EN ((unsigned int) 0x1 <<  1) // (SYS) Enable External Oscillator
#define AT91C_SLCKSEL_OSC32BYP ((unsigned int) 0x1 <<  2) // (SYS) Bypass External Oscillator
#define AT91C_SLCKSEL_OSCSEL  ((unsigned int) 0x1 <<  3) // (SYS) OSC Selection

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
	AT91_REG	 EBI_DUMMY; 	// Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;


// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
// *****************************************************************************
typedef struct _AT91S_SDRAMC {
	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;

// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
#define AT91C_SDRAMC_MODE     ((unsigned int) 0xF <<  0) // (SDRAMC) Mode
#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           ((unsigned int) 0x0) // (SDRAMC) Normal Mode
#define 	AT91C_SDRAMC_MODE_NOP_CMD              ((unsigned int) 0x1) // (SDRAMC) Issue a NOP Command at every access
#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          ((unsigned int) 0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define 	AT91C_SDRAMC_MODE_LMR_CMD              ((unsigned int) 0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define 	AT91C_SDRAMC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRAMC) Issue a Refresh
#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          ((unsigned int) 0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define 	AT91C_SDRAMC_MODE_DEEP_CMD             ((unsigned int) 0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
#define AT91C_SDRAMC_COUNT    ((unsigned int) 0xFFF <<  0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
#define AT91C_SDRAMC_NC       ((unsigned int) 0x3 <<  0) // (SDRAMC) Number of Column Bits
#define 	AT91C_SDRAMC_NC_8                    ((unsigned int) 0x0) // (SDRAMC) 8 Bits
#define 	AT91C_SDRAMC_NC_9                    ((unsigned int) 0x1) // (SDRAMC) 9 Bits
#define 	AT91C_SDRAMC_NC_10                   ((unsigned int) 0x2) // (SDRAMC) 10 Bits
#define 	AT91C_SDRAMC_NC_11                   ((unsigned int) 0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR       ((unsigned int) 0x3 <<  2) // (SDRAMC) Number of Row Bits
#define 	AT91C_SDRAMC_NR_11                   ((unsigned int) 0x0 <<  2) // (SDRAMC) 11 Bits
#define 	AT91C_SDRAMC_NR_12                   ((unsigned int) 0x1 <<  2) // (SDRAMC) 12 Bits
#define 	AT91C_SDRAMC_NR_13                   ((unsigned int) 0x2 <<  2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB       ((unsigned int) 0x1 <<  4) // (SDRAMC) Number of Banks
#define 	AT91C_SDRAMC_NB_2_BANKS              ((unsigned int) 0x0 <<  4) // (SDRAMC) 2 banks
#define 	AT91C_SDRAMC_NB_4_BANKS              ((unsigned int) 0x1 <<  4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS      ((unsigned int) 0x3 <<  5) // (SDRAMC) CAS Latency
#define 	AT91C_SDRAMC_CAS_2                    ((unsigned int) 0x2 <<  5) // (SDRAMC) 2 cycles
#define 	AT91C_SDRAMC_CAS_3                    ((unsigned int) 0x3 <<  5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW      ((unsigned int) 0x1 <<  7) // (SDRAMC) Data Bus Width
#define 	AT91C_SDRAMC_DBW_32_BITS              ((unsigned int) 0x0 <<  7) // (SDRAMC) 32 Bits datas bus
#define 	AT91C_SDRAMC_DBW_16_BITS              ((unsigned int) 0x1 <<  7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR      ((unsigned int) 0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles
#define 	AT91C_SDRAMC_TWR_0                    ((unsigned int) 0x0 <<  8) // (SDRAMC) Value :  0
#define 	AT91C_SDRAMC_TWR_1                    ((unsigned int) 0x1 <<  8) // (SDRAMC) Value :  1
#define 	AT91C_SDRAMC_TWR_2                    ((unsigned int) 0x2 <<  8) // (SDRAMC) Value :  2
#define 	AT91C_SDRAMC_TWR_3                    ((unsigned int) 0x3 <<  8) // (SDRAMC) Value :  3
#define 	AT91C_SDRAMC_TWR_4                    ((unsigned int) 0x4 <<  8) // (SDRAMC) Value :  4
#define 	AT91C_SDRAMC_TWR_5                    ((unsigned int) 0x5 <<  8) // (SDRAMC) Value :  5
#define 	AT91C_SDRAMC_TWR_6                    ((unsigned int) 0x6 <<  8) // (SDRAMC) Value :  6
#define 	AT91C_SDRAMC_TWR_7                    ((unsigned int) 0x7 <<  8) // (SDRAMC) Value :  7
#define 	AT91C_SDRAMC_TWR_8                    ((unsigned int) 0x8 <<  8) // (SDRAMC) Value :  8
#define 	AT91C_SDRAMC_TWR_9                    ((unsigned int) 0x9 <<  8) // (SDRAMC) Value :  9
#define 	AT91C_SDRAMC_TWR_10                   ((unsigned int) 0xA <<  8) // (SDRAMC) Value : 10
#define 	AT91C_SDRAMC_TWR_11                   ((unsigned int) 0xB <<  8) // (SDRAMC) Value : 11
#define 	AT91C_SDRAMC_TWR_12                   ((unsigned int) 0xC <<  8) // (SDRAMC) Value : 12
#define 	AT91C_SDRAMC_TWR_13                   ((unsigned int) 0xD <<  8) // (SDRAMC) Value : 13
#define 	AT91C_SDRAMC_TWR_14                   ((unsigned int) 0xE <<  8) // (SDRAMC) Value : 14
#define 	AT91C_SDRAMC_TWR_15                   ((unsigned int) 0xF <<  8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC      ((unsigned int) 0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles