at91sam9263.h

试用于arm9 at91sram9260开发板的uboot程序

/* ***************************************************************************** */
typedef struct _AT91S_MATRIX {
	AT91_REG	 MATRIX_MCFG0; 	/*  Master Configuration Register 0 (rom) */
	AT91_REG	 MATRIX_MCFG1; 	/*  Master Configuration Register 1 (htcm) */
	AT91_REG	 MATRIX_MCFG2; 	/*  Master Configuration Register 2 (gps_tcm) */
	AT91_REG	 MATRIX_MCFG3; 	/*  Master Configuration Register 3 (hperiphs) */
	AT91_REG	 MATRIX_MCFG4; 	/*  Master Configuration Register 4 (ebi0) */
	AT91_REG	 MATRIX_MCFG5; 	/*  Master Configuration Register 5 (ebi1) */
	AT91_REG	 MATRIX_MCFG6; 	/*  Master Configuration Register 6 (bridge) */
	AT91_REG	 MATRIX_MCFG7; 	/*  Master Configuration Register 7 (gps) */
	AT91_REG	 Reserved0[8]; 	/* */
	AT91_REG	 MATRIX_SCFG0; 	/*  Slave Configuration Register 0 (rom) */
	AT91_REG	 MATRIX_SCFG1; 	/*  Slave Configuration Register 1 (htcm) */
	AT91_REG	 MATRIX_SCFG2; 	/*  Slave Configuration Register 2 (gps_tcm) */
	AT91_REG	 MATRIX_SCFG3; 	/*  Slave Configuration Register 3 (hperiphs) */
	AT91_REG	 MATRIX_SCFG4; 	/*  Slave Configuration Register 4 (ebi0) */
	AT91_REG	 MATRIX_SCFG5; 	/*  Slave Configuration Register 5 (ebi1) */
	AT91_REG	 MATRIX_SCFG6; 	/*  Slave Configuration Register 6 (bridge) */
	AT91_REG	 MATRIX_SCFG7; 	/*  Slave Configuration Register 7 (gps) */
	AT91_REG	 Reserved1[8]; 	/* */
	AT91_REG	 MATRIX_PRAS0; 	/*  PRAS0 (ram0) */
	AT91_REG	 MATRIX_PRBS0; 	/*  PRBS0 (ram0) */
	AT91_REG	 MATRIX_PRAS1; 	/*  PRAS1 (ram1) */
	AT91_REG	 MATRIX_PRBS1; 	/*  PRBS1 (ram1) */
	AT91_REG	 MATRIX_PRAS2; 	/*  PRAS2 (ram2) */
	AT91_REG	 MATRIX_PRBS2; 	/*  PRBS2 (ram2) */
	AT91_REG	 Reserved2[26]; 	/* */
	AT91_REG	 MATRIX_MRCR; 	/*  Master Remp Control Register */
	AT91_REG	 Reserved3[3]; 	/* */
	AT91_REG	 MATRIX_ROM; 	/*  Slave 0 (rom) Special Function Register */
	AT91_REG	 MATRIX_TCMR; 	/*  Slave 1 (htcm) Special Function Register */
	AT91_REG	 MATRIX_GPSTCM; 	/*  Slave 2 (gps_tcm) Special Function Register */
	AT91_REG	 MATRIX_USBPCR; 	/*  Slave 3 (hperiphs) Special Function Register */
	AT91_REG	 MATRIX_EBI0; 	/*  Slave 4 (ebi0) Special Function Register */
	AT91_REG	 MATRIX_EBI1; 	/*  Slave 5 (ebi1) Special Function Register */
	AT91_REG	 MATRIX_BRIDGE; 	/*  Slave 6 (bridge) Special Function Register */
	AT91_REG	 MATRIX_GPS; 	/*  Slave 7 (gps) Special Function Register */
	AT91_REG	 Reserved4[51]; 	/* */
	AT91_REG	 MATRIX_VERSION; 	/*  Version Register */
} AT91S_MATRIX, *AT91PS_MATRIX;

/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom -------- */
#define AT91C_MATRIX_RCA926I  ((unsigned int) 0x1 <<  0) /* (MATRIX) Remap Command for ARM926EJ-S Instruction Master */
#define AT91C_MATRIX_RCA926D  ((unsigned int) 0x1 <<  1) /* (MATRIX) Remap Command for ARM926EJ-S Data Master */
/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm -------- */
/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm -------- */
/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs -------- */
/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 -------- */
/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 -------- */
/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge -------- */
/* -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps -------- */
/* -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- */
#define AT91C_MATRIX_SLOT_CYCLE ((unsigned int) 0xFF <<  0) /* (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE ((unsigned int) 0x3 << 16) /* (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           ((unsigned int) 0x0 << 16) /* (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         ((unsigned int) 0x1 << 16) /* (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        ((unsigned int) 0x2 << 16) /* (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR0 ((unsigned int) 0x7 << 18) /* (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              ((unsigned int) 0x0 << 18) /* (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              ((unsigned int) 0x1 << 18) /* (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                ((unsigned int) 0x2 << 18) /* (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 ((unsigned int) 0x3 << 18) /* (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_UHP                  ((unsigned int) 0x4 << 18) /* (MATRIX) UHP Master is Default Master */
/* -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- */
#define AT91C_MATRIX_FIXED_DEFMSTR1 ((unsigned int) 0x7 << 18) /* (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              ((unsigned int) 0x0 << 18) /* (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              ((unsigned int) 0x1 << 18) /* (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                ((unsigned int) 0x2 << 18) /* (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 ((unsigned int) 0x3 << 18) /* (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_UHP                  ((unsigned int) 0x4 << 18) /* (MATRIX) UHP Master is Default Master */
/* -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- */
#define AT91C_MATRIX_FIXED_DEFMSTR2 ((unsigned int) 0x1 << 18) /* (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              ((unsigned int) 0x0 << 18) /* (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              ((unsigned int) 0x1 << 18) /* (MATRIX) ARM926EJ-S Data Master is Default Master */
/* -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- */
#define AT91C_MATRIX_FIXED_DEFMSTR3 ((unsigned int) 0x7 << 18) /* (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              ((unsigned int) 0x0 << 18) /* (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              ((unsigned int) 0x1 << 18) /* (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                ((unsigned int) 0x2 << 18) /* (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 ((unsigned int) 0x3 << 18) /* (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_UHP                  ((unsigned int) 0x4 << 18) /* (MATRIX) UHP Master is Default Master */
/* -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- */
#define AT91C_MATRIX_FIXED_DEFMSTR4 ((unsigned int) 0x3 << 18) /* (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              ((unsigned int) 0x0 << 18) /* (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              ((unsigned int) 0x1 << 18) /* (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                ((unsigned int) 0x2 << 18) /* (MATRIX) HPDC3 Master is Default Master */
/* -------- MATRIX_TCMR : (MATRIX Offset: 0x114) TCM (Slave 0) Special Function Register -------- */
#define AT91C_MATRIX_ITCM_SIZE ((unsigned int) 0xF <<  0) /* (MATRIX) Size of ITCM enabled memory block */
#define 	AT91C_MATRIX_ITCM_SIZE_0KB                  ((unsigned int) 0x0) /* (MATRIX) 0 KB (No ITCM Memory) */
#define 	AT91C_MATRIX_ITCM_SIZE_16KB                 ((unsigned int) 0x5) /* (MATRIX) 16 KB */
#define 	AT91C_MATRIX_ITCM_SIZE_32KB                 ((unsigned int) 0x6) /* (MATRIX) 32 KB */
#define 	AT91C_MATRIX_ITCM_SIZE_64KB                 ((unsigned int) 0x7) /* (MATRIX) 64 KB */
#define AT91C_MATRIX_DTCM_SIZE ((unsigned int) 0xF <<  4) /* (MATRIX) Size of DTCM enabled memory block */
#define 	AT91C_MATRIX_DTCM_SIZE_0KB                  ((unsigned int) 0x0 <<  4) /* (MATRIX) 0 KB (No DTCM Memory) */
#define 	AT91C_MATRIX_DTCM_SIZE_16KB                 ((unsigned int) 0x5 <<  4) /* (MATRIX) 16 KB */
#define 	AT91C_MATRIX_DTCM_SIZE_32KB                 ((unsigned int) 0x6 <<  4) /* (MATRIX) 32 KB */
#define 	AT91C_MATRIX_DTCM_SIZE_64KB                 ((unsigned int) 0x7 <<  4) /* (MATRIX) 64 KB */
#define AT91C_MATRIX_RM       ((unsigned int) 0xF <<  8) /* (MATRIX) Read Margin registers */
/* -------- MATRIX_USBPCR : (MATRIX Offset: 0x11c) USB Pad Control Register -------- */
#define AT91C_MATRIX_USBPCR_PUON ((unsigned int) 0x1 << 30) /* (MATRIX) PullUp On */
#define AT91C_MATRIX_USBPCR_PUIDLE ((unsigned int) 0x1 << 31) /* (MATRIX) PullUp Idle */
/* -------- MATRIX_EBI0 : (MATRIX Offset: 0x120) EBI (Slave 3) Special Function Register -------- */
#define AT91C_MATRIX_CS1A     ((unsigned int) 0x1 <<  1) /* (MATRIX) Chip Select 1 Assignment */
#define 	AT91C_MATRIX_CS1A_SMC                  ((unsigned int) 0x0 <<  1) /* (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. */
#define 	AT91C_MATRIX_CS1A_SDRAMC               ((unsigned int) 0x1 <<  1) /* (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. */
#define AT91C_MATRIX_CS3A     ((unsigned int) 0x1 <<  3) /* (MATRIX) Chip Select 3 Assignment */
#define 	AT91C_MATRIX_CS3A_SMC                  ((unsigned int) 0x0 <<  3) /* (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. */
#define 	AT91C_MATRIX_CS3A_SM                   ((unsigned int) 0x1 <<  3) /* (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
#define AT91C_MATRIX_CS4A     ((unsigned int) 0x1 <<  4) /* (MATRIX) Chip Select 4 Assignment */
#define 	AT91C_MATRIX_CS4A_SMC                  ((unsigned int) 0x0 <<  4) /* (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. */
#define 	AT91C_MATRIX_CS4A_CF                   ((unsigned int) 0x1 <<  4) /* (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. */
#define AT91C_MATRIX_CS5A     ((unsigned int) 0x1 <<  5) /* (MATRIX) Chip Select 5 Assignment */
#define 	AT91C_MATRIX_CS5A_SMC                  ((unsigned int) 0x0 <<  5) /* (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC */
#define 	AT91C_MATRIX_CS5A_CF                   ((unsigned int) 0x1 <<  5) /* (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. */
#define AT91C_MATRIX_DBPUC    ((unsigned int) 0x1 <<  8) /* (MATRIX) Data Bus Pull-up Configuration */
/* -------- MATRIX_EBI1 : (MATRIX Offset: 0x124) Slave 5 Special Function Register -------- */
#define AT91C_MATRIX_EB1_CS1  ((unsigned int) 0x1 <<  1) /* (MATRIX) EBI1 Chip Select 1 Assignment */
#define 	AT91C_MATRIX_EB1_CS1_SMC                  ((unsigned int) 0x0 <<  1) /* (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. */
#define 	AT91C_MATRIX_EB1_CS1_SDRAMC               ((unsigned int) 0x1 <<  1) /* (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. */
#define AT91C_MATRIX_EB1_CS2  ((unsigned int) 0x1 <<  3) /* (MATRIX) EBI1 Chip Select 2 Assignment */
#define 	AT91C_MATRIX_EB1_CS2_SMC                  ((unsigned int) 0x0 <<  3) /* (MATRIX) Chip Select 2 is assigned to the Static Memory Controller. */
#define 	AT91C_MATRIX_EB1_CS2_SM                   ((unsigned int) 0x1 <<  3) /* (MATRIX) Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
#define AT91C_MATRIX1_EB1_CFEN ((unsigned int) 0x3 <<  4) /* (MATRIX) EBI1 Compact Flash enable */
#define AT91C_HMATRIX1_EB1_PULLDATA ((unsigned int) 0x1 <<  8) /* (MATRIX) EBI1 pullup data enable */

/* ***************************************************************************** */
/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
/* ***************************************************************************** */
typedef struct _AT91S_PDC {
	AT91_REG	 PDC_RPR; 	/* Receive Pointer Register */
	AT91_REG	 PDC_RCR; 	/* Receive Counter Register */
	AT91_REG	 PDC_TPR; 	/* Transmit Pointer Register */
	AT91_REG	 PDC_TCR; 	/* Transmit Counter Register */
	AT91_REG	 PDC_RNPR; 	/* Receive Next Pointer Register */
	AT91_REG	 PDC_RNCR; 	/* Receive Next Counter Register */
	AT91_REG	 PDC_TNPR; 	/* Transmit Next Pointer Register */
	AT91_REG	 PDC_TNCR; 	/* Transmit Next Counter Register */
	AT91_REG	 PDC_PTCR; 	/* PDC Transfer Control Register */
	AT91_REG	 PDC_PTSR; 	/* PDC Transfer Status Register */
} AT91S_PDC, *AT91PS_PDC;

/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */

/* ***************************************************************************** */
/*              SOFTWARE API DEFINITION  FOR Debug Unit */
/* ***************************************************************************** */
typedef struct _AT91S_DBGU {
	AT91_REG	 DBGU_CR; 	/* Control Register */
	AT91_REG	 DBGU_MR; 	/* Mode Register */
	AT91_REG	 DBGU_IER; 	/* Interrupt Enable Register */
	AT91_REG	 DBGU_IDR; 	/* Interrupt Disable Register */
	AT91_REG	 DBGU_IMR; 	/* Interrupt Mask Register */
	AT91_REG	 DBGU_CSR; 	/* Channel Status Register */
	AT91_REG	 DBGU_RHR; 	/* Receiver Holding Register */
	AT91_REG	 DBGU_THR; 	/* Transmitter Holding Register */
	AT91_REG	 DBGU_BRGR; 	/* Baud Rate Generator Register */
	AT91_REG	 Reserved0[7]; 	/* */
	AT91_REG	 DBGU_CIDR; 	/* Chip ID Register */
	AT91_REG	 DBGU_EXID; 	/* Chip ID Extension Register */
	AT91_REG	 DBGU_FNTR; 	/* Force NTRST Register */
	AT91_REG	 Reserved1[45]; 	/* */
	AT91_REG	 DBGU_RPR; 	/* Receive Pointer Register */
	AT91_REG	 DBGU_RCR; 	/* Receive Counter Register */
	AT91_REG	 DBGU_TPR; 	/* Transmit Pointer Register */
	AT91_REG	 DBGU_TCR; 	/* Transmit Counter Register */
	AT91_REG	 DBGU_RNPR; 	/* Receive Next Pointer Register */
	AT91_REG	 DBGU_RNCR; 	/* Receive Next Counter Register */
	AT91_REG	 DBGU_TNPR; 	/* Transmit Next Pointer Register */
	AT91_REG	 DBGU_TNCR; 	/* Transmit Next Counter Register */
	AT91_REG	 DBGU_PTCR; 	/* PDC Transfer Control Register */
	AT91_REG	 DBGU_PTSR; 	/* PDC Transfer Status Register */
} AT91S_DBGU, *AT91PS_DBGU;

/* -------- DBGU_CR : (DBGU Offset: 0x0) Debu