at91sam9263.h

试用于arm9 at91sram9260开发板的uboot程序

/*  ----------------------------------------------------------------------------
 *          ATMEL Microcontroller Software Support  -  ROUSSET  -
 *  ----------------------------------------------------------------------------
 *  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 *  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 *  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 *  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 *  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *  ----------------------------------------------------------------------------
 * File Name           : AT91SAM9263.h
 * Object              : AT91SAM9263 definitions
 * Generated           : AT91 SW Application Group  08/29/2005 (13:14:06)
 *
 *  ----------------------------------------------------------------------------
*/

#ifndef AT91SAM9263_H
#define AT91SAM9263_H

typedef volatile unsigned int AT91_REG;/* Hardware register definition */

/* ***************************************************************************** */
/*              SOFTWARE API DEFINITION  FOR System Peripherals */
/* ***************************************************************************** */
typedef struct _AT91S_SYS {
	AT91_REG	 SYS_ECC0; 	/* ECC 0 */
	AT91_REG	 Reserved0[127];
	AT91_REG	 SYS_SDRAMC0_MR; 	/* SDRAM Controller Mode Register */
	AT91_REG	 SYS_SDRAMC0_TR; 	/* SDRAM Controller Refresh Timer Register */
	AT91_REG	 SYS_SDRAMC0_CR; 	/* SDRAM Controller Configuration Register */
	AT91_REG	 SYS_SDRAMC0_HSR; 	/* SDRAM Controller High Speed Register */
	AT91_REG	 SYS_SDRAMC0_LPR; 	/* SDRAM Controller Low Power Register */
	AT91_REG	 SYS_SDRAMC0_IER; 	/* SDRAM Controller Interrupt Enable Register */
	AT91_REG	 SYS_SDRAMC0_IDR; 	/* SDRAM Controller Interrupt Disable Register */
	AT91_REG	 SYS_SDRAMC0_IMR; 	/* SDRAM Controller Interrupt Mask Register */
	AT91_REG	 SYS_SDRAMC0_ISR; 	/* SDRAM Controller Interrupt Mask Register */
	AT91_REG	 SYS_SDRAMC0_MDR; 	/* SDRAM Memory Device Register */
	AT91_REG	 Reserved1[118];
	AT91_REG	 SYS_SMC0_SETUP0; 	/*  Setup Register for CS 0 */
	AT91_REG	 SYS_SMC0_PULSE0; 	/*  Pulse Register for CS 0 */
	AT91_REG	 SYS_SMC0_CYCLE0; 	/*  Cycle Register for CS 0 */
	AT91_REG	 SYS_SMC0_CTRL0; 	/*  Control Register for CS 0 */
	AT91_REG	 SYS_SMC0_SETUP1; 	/*  Setup Register for CS 1 */
	AT91_REG	 SYS_SMC0_PULSE1; 	/*  Pulse Register for CS 1 */
	AT91_REG	 SYS_SMC0_CYCLE1; 	/*  Cycle Register for CS 1 */
	AT91_REG	 SYS_SMC0_CTRL1; 	/*  Control Register for CS 1 */
	AT91_REG	 SYS_SMC0_SETUP2; 	/*  Setup Register for CS 2 */
	AT91_REG	 SYS_SMC0_PULSE2; 	/*  Pulse Register for CS 2 */
	AT91_REG	 SYS_SMC0_CYCLE2; 	/*  Cycle Register for CS 2 */
	AT91_REG	 SYS_SMC0_CTRL2; 	/*  Control Register for CS 2 */
	AT91_REG	 SYS_SMC0_SETUP3; 	/*  Setup Register for CS 3 */
	AT91_REG	 SYS_SMC0_PULSE3; 	/*  Pulse Register for CS 3 */
	AT91_REG	 SYS_SMC0_CYCLE3; 	/*  Cycle Register for CS 3 */
	AT91_REG	 SYS_SMC0_CTRL3; 	/*  Control Register for CS 3 */
	AT91_REG	 SYS_SMC0_SETUP4; 	/*  Setup Register for CS 4 */
	AT91_REG	 SYS_SMC0_PULSE4; 	/*  Pulse Register for CS 4 */
	AT91_REG	 SYS_SMC0_CYCLE4; 	/*  Cycle Register for CS 4 */
	AT91_REG	 SYS_SMC0_CTRL4; 	/*  Control Register for CS 4 */
	AT91_REG	 SYS_SMC0_SETUP5; 	/*  Setup Register for CS 5 */
	AT91_REG	 SYS_SMC0_PULSE5; 	/*  Pulse Register for CS 5 */
	AT91_REG	 SYS_SMC0_CYCLE5; 	/*  Cycle Register for CS 5 */
	AT91_REG	 SYS_SMC0_CTRL5; 	/*  Control Register for CS 5 */
	AT91_REG	 SYS_SMC0_SETUP6; 	/*  Setup Register for CS 6 */
	AT91_REG	 SYS_SMC0_PULSE6; 	/*  Pulse Register for CS 6 */
	AT91_REG	 SYS_SMC0_CYCLE6; 	/*  Cycle Register for CS 6 */
	AT91_REG	 SYS_SMC0_CTRL6; 	/*  Control Register for CS 6 */
	AT91_REG	 SYS_SMC0_SETUP7; 	/*  Setup Register for CS 7 */
	AT91_REG	 SYS_SMC0_PULSE7; 	/*  Pulse Register for CS 7 */
	AT91_REG	 SYS_SMC0_CYCLE7; 	/*  Cycle Register for CS 7 */
	AT91_REG	 SYS_SMC0_CTRL7; 	/*  Control Register for CS 7 */
	AT91_REG	 Reserved2[96]; 	/* */
	AT91_REG	 SYS_ECC1; 	/* ECC 0 */
	AT91_REG	 Reserved3[127]; 	/* */
	AT91_REG	 SYS_SDRAMC1_MR; 	/* SDRAM Controller Mode Register */
	AT91_REG	 SYS_SDRAMC1_TR; 	/* SDRAM Controller Refresh Timer Register */
	AT91_REG	 SYS_SDRAMC1_CR; 	/* SDRAM Controller Configuration Register */
	AT91_REG	 SYS_SDRAMC1_HSR; 	/* SDRAM Controller High Speed Register */
	AT91_REG	 SYS_SDRAMC1_LPR; 	/* SDRAM Controller Low Power Register */
	AT91_REG	 SYS_SDRAMC1_IER; 	/* SDRAM Controller Interrupt Enable Register */
	AT91_REG	 SYS_SDRAMC1_IDR; 	/* SDRAM Controller Interrupt Disable Register */
	AT91_REG	 SYS_SDRAMC1_IMR; 	/* SDRAM Controller Interrupt Mask Register */
	AT91_REG	 SYS_SDRAMC1_ISR; 	/* SDRAM Controller Interrupt Mask Register */
	AT91_REG	 SYS_SDRAMC1_MDR; 	/* SDRAM Memory Device Register */
	AT91_REG	 Reserved4[118]; 	/* */
	AT91_REG	 SYS_SMC1_SETUP0; 	/*  Setup Register for CS 0 */
	AT91_REG	 SYS_SMC1_PULSE0; 	/*  Pulse Register for CS 0 */
	AT91_REG	 SYS_SMC1_CYCLE0; 	/*  Cycle Register for CS 0 */
	AT91_REG	 SYS_SMC1_CTRL0; 	/*  Control Register for CS 0 */
	AT91_REG	 SYS_SMC1_SETUP1; 	/*  Setup Register for CS 1 */
	AT91_REG	 SYS_SMC1_PULSE1; 	/*  Pulse Register for CS 1 */
	AT91_REG	 SYS_SMC1_CYCLE1; 	/*  Cycle Register for CS 1 */
	AT91_REG	 SYS_SMC1_CTRL1; 	/*  Control Register for CS 1 */
	AT91_REG	 SYS_SMC1_SETUP2; 	/*  Setup Register for CS 2 */
	AT91_REG	 SYS_SMC1_PULSE2; 	/*  Pulse Register for CS 2 */
	AT91_REG	 SYS_SMC1_CYCLE2; 	/*  Cycle Register for CS 2 */
	AT91_REG	 SYS_SMC1_CTRL2; 	/*  Control Register for CS 2 */
	AT91_REG	 SYS_SMC1_SETUP3; 	/*  Setup Register for CS 3 */
	AT91_REG	 SYS_SMC1_PULSE3; 	/*  Pulse Register for CS 3 */
	AT91_REG	 SYS_SMC1_CYCLE3; 	/*  Cycle Register for CS 3 */
	AT91_REG	 SYS_SMC1_CTRL3; 	/*  Control Register for CS 3 */
	AT91_REG	 SYS_SMC1_SETUP4; 	/*  Setup Register for CS 4 */
	AT91_REG	 SYS_SMC1_PULSE4; 	/*  Pulse Register for CS 4 */
	AT91_REG	 SYS_SMC1_CYCLE4; 	/*  Cycle Register for CS 4 */
	AT91_REG	 SYS_SMC1_CTRL4; 	/*  Control Register for CS 4 */
	AT91_REG	 SYS_SMC1_SETUP5; 	/*  Setup Register for CS 5 */
	AT91_REG	 SYS_SMC1_PULSE5; 	/*  Pulse Register for CS 5 */
	AT91_REG	 SYS_SMC1_CYCLE5; 	/*  Cycle Register for CS 5 */
	AT91_REG	 SYS_SMC1_CTRL5; 	/*  Control Register for CS 5 */
	AT91_REG	 SYS_SMC1_SETUP6; 	/*  Setup Register for CS 6 */
	AT91_REG	 SYS_SMC1_PULSE6; 	/*  Pulse Register for CS 6 */
	AT91_REG	 SYS_SMC1_CYCLE6; 	/*  Cycle Register for CS 6 */
	AT91_REG	 SYS_SMC1_CTRL6; 	/*  Control Register for CS 6 */
	AT91_REG	 SYS_SMC1_SETUP7; 	/*  Setup Register for CS 7 */
	AT91_REG	 SYS_SMC1_PULSE7; 	/*  Pulse Register for CS 7 */
	AT91_REG	 SYS_SMC1_CYCLE7; 	/*  Cycle Register for CS 7 */
	AT91_REG	 SYS_SMC1_CTRL7; 	/*  Control Register for CS 7 */
	AT91_REG	 Reserved5[96]; 	/* */
	AT91_REG	 SYS_MATRIX_MCFG0; 	/*  Master Configuration Register 0 (rom) */
	AT91_REG	 SYS_MATRIX_MCFG1; 	/*  Master Configuration Register 1 (htcm) */
	AT91_REG	 SYS_MATRIX_MCFG2; 	/*  Master Configuration Register 2 (gps_tcm) */
	AT91_REG	 SYS_MATRIX_MCFG3; 	/*  Master Configuration Register 3 (hperiphs) */
	AT91_REG	 SYS_MATRIX_MCFG4; 	/*  Master Configuration Register 4 (ebi0) */
	AT91_REG	 SYS_MATRIX_MCFG5; 	/*  Master Configuration Register 5 (ebi1) */
	AT91_REG	 SYS_MATRIX_MCFG6; 	/*  Master Configuration Register 6 (bridge) */
	AT91_REG	 SYS_MATRIX_MCFG7; 	/*  Master Configuration Register 7 (gps) */
	AT91_REG	 Reserved6[8]; 	/* */
	AT91_REG	 SYS_MATRIX_SCFG0; 	/*  Slave Configuration Register 0 (rom) */
	AT91_REG	 SYS_MATRIX_SCFG1; 	/*  Slave Configuration Register 1 (htcm) */
	AT91_REG	 SYS_MATRIX_SCFG2; 	/*  Slave Configuration Register 2 (gps_tcm) */
	AT91_REG	 SYS_MATRIX_SCFG3; 	/*  Slave Configuration Register 3 (hperiphs) */
	AT91_REG	 SYS_MATRIX_SCFG4; 	/*  Slave Configuration Register 4 (ebi0) */
	AT91_REG	 SYS_MATRIX_SCFG5; 	/*  Slave Configuration Register 5 (ebi1) */
	AT91_REG	 SYS_MATRIX_SCFG6; 	/*  Slave Configuration Register 6 (bridge) */
	AT91_REG	 SYS_MATRIX_SCFG7; 	/*  Slave Configuration Register 7 (gps) */
	AT91_REG	 Reserved7[8]; 	/* */
	AT91_REG	 SYS_MATRIX_PRAS0; 	/*  PRAS0 (ram0) */
	AT91_REG	 SYS_MATRIX_PRBS0; 	/*  PRBS0 (ram0) */
	AT91_REG	 SYS_MATRIX_PRAS1; 	/*  PRAS1 (ram1) */
	AT91_REG	 SYS_MATRIX_PRBS1; 	/*  PRBS1 (ram1) */
	AT91_REG	 SYS_MATRIX_PRAS2; 	/*  PRAS2 (ram2) */
	AT91_REG	 SYS_MATRIX_PRBS2; 	/*  PRBS2 (ram2) */
	AT91_REG	 Reserved8[26]; 	/* */
	AT91_REG	 SYS_MATRIX_MRCR; 	/*  Master Remp Control Register */
	AT91_REG	 Reserved9[3]; 	/* */
	AT91_REG	 SYS_MATRIX_ROM; 	/*  Slave 0 (rom) Special Function Register */
	AT91_REG	 SYS_MATRIX_TCMR; 	/*  Slave 1 (htcm) Special Function Register */
	AT91_REG	 SYS_MATRIX_GPSTCM; 	/*  Slave 2 (gps_tcm) Special Function Register */
	AT91_REG	 SYS_MATRIX_USBPCR; 	/*  Slave 3 (hperiphs) Special Function Register */
	AT91_REG	 SYS_MATRIX_EBI0; 	/*  Slave 4 (ebi0) Special Function Register */
	AT91_REG	 SYS_MATRIX_EBI1; 	/*  Slave 5 (ebi1) Special Function Register */
	AT91_REG	 SYS_MATRIX_BRIDGE; 	/*  Slave 6 (bridge) Special Function Register */
	AT91_REG	 SYS_MATRIX_GPS; 	/*  Slave 7 (gps) Special Function Register */
	AT91_REG	 Reserved10[51]; 	/* */
	AT91_REG	 SYS_MATRIX_VERSION; 	/*  Version Register */
	AT91_REG	 SYS_DBGU_CR; 	/* Control Register */
	AT91_REG	 SYS_DBGU_MR; 	/* Mode Register */
	AT91_REG	 SYS_DBGU_IER; 	/* Interrupt Enable Register */
	AT91_REG	 SYS_DBGU_IDR; 	/* Interrupt Disable Register */
	AT91_REG	 SYS_DBGU_IMR; 	/* Interrupt Mask Register */
	AT91_REG	 SYS_DBGU_CSR; 	/* Channel Status Register */
	AT91_REG	 SYS_DBGU_RHR; 	/* Receiver Holding Register */
	AT91_REG	 SYS_DBGU_THR; 	/* Transmitter Holding Register */
	AT91_REG	 SYS_DBGU_BRGR; 	/* Baud Rate Generator Register */
	AT91_REG	 Reserved11[7]; 	/* */
	AT91_REG	 SYS_DBGU_CIDR; 	/* Chip ID Register */
	AT91_REG	 SYS_DBGU_EXID; 	/* Chip ID Extension Register */
	AT91_REG	 SYS_DBGU_FNTR; 	/* Force NTRST Register */
	AT91_REG	 Reserved12[45]; 	/* */
	AT91_REG	 SYS_DBGU_RPR; 	/* Receive Pointer Register */
	AT91_REG	 SYS_DBGU_RCR; 	/* Receive Counter Register */
	AT91_REG	 SYS_DBGU_TPR; 	/* Transmit Pointer Register */
	AT91_REG	 SYS_DBGU_TCR; 	/* Transmit Counter Register */
	AT91_REG	 SYS_DBGU_RNPR; 	/* Receive Next Pointer Register */
	AT91_REG	 SYS_DBGU_RNCR; 	/* Receive Next Counter Register */