📄 msp430xe42x.h
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#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
#define FCTL1_ (0x0128) /* FLASH Control 1 */
DEFW( FCTL1 , FCTL1_)
#define FCTL2_ (0x012A) /* FLASH Control 2 */
DEFW( FCTL2 , FCTL2_)
#define FCTL3_ (0x012C) /* FLASH Control 3 */
DEFW( FCTL3 , FCTL3_)
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#ifndef FN2
#define FN2 (0x0004)
#endif
#ifndef FN3
#define FN3 (0x0008)
#endif
#ifndef FN4
#define FN4 (0x0010)
#endif
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
#define WAIT (0x0008) /* Wait flag for segment write */
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020) /* Flash Emergency Exit */
/************************************************************
* HARDWARE MULTIPLIER
************************************************************/
#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */
#define MPY_ (0x0130) /* Multiply Unsigned/Operand 1 */
DEFW( MPY , MPY_)
#define MPYS_ (0x0132) /* Multiply Signed/Operand 1 */
DEFW( MPYS , MPYS_)
#define MAC_ (0x0134) /* Multiply Unsigned and Accumulate/Operand 1 */
DEFW( MAC , MAC_)
#define MACS_ (0x0136) /* Multiply Signed and Accumulate/Operand 1 */
DEFW( MACS , MACS_)
#define OP2_ (0x0138) /* Operand 2 */
DEFW( OP2 , OP2_)
#define RESLO_ (0x013A) /* Result Low Word */
DEFW( RESLO , RESLO_)
#define RESHI_ (0x013C) /* Result High Word */
DEFW( RESHI , RESHI_)
#define SUMEXT_ (0x013E) /* Sum Extend */
READ_ONLY DEFW( SUMEXT , SUMEXT_)
/************************************************************
* SD16 - Sigma Delta 16 Bit
************************************************************/
#define __MSP430_HAS_SD16_3__ /* Definition to show that Module is available */
#define SD16INCTL0_ (0x00B0) /* SD16 Input Control Register Channel 0 */
DEFC( SD16INCTL0 , SD16INCTL0_)
#define SD16INCTL1_ (0x00B1) /* SD16 Input Control Register Channel 1 */
DEFC( SD16INCTL1 , SD16INCTL1_)
#define SD16INCTL2_ (0x00B2) /* SD16 Input Control Register Channel 2 */
DEFC( SD16INCTL2 , SD16INCTL2_)
#define SD16PRE0_ (0x00B8) /* SD16 Preload Register Channel 0 */
DEFC( SD16PRE0 , SD16PRE0_)
#define SD16PRE1_ (0x00B9) /* SD16 Preload Register Channel 1 */
DEFC( SD16PRE1 , SD16PRE1_)
#define SD16PRE2_ (0x00BA) /* SD16 Preload Register Channel 2 */
DEFC( SD16PRE2 , SD16PRE2_)
#define SD16CONF0_ (0x00B7) /* SD16 Internal Configuration Register 0 */
DEFC( SD16CONF0 , SD16CONF0_)
#define SD16CONF1_ (0x00BF) /* SD16 Internal Configuration Register 1 */
DEFC( SD16CONF1 , SD16CONF1_)
/* Please use only the recommended settings */
#define SD16CTL_ (0x0100) /* Sigma Delta ADC 16 Control Register */
DEFW( SD16CTL , SD16CTL_)
#define SD16CCTL0_ (0x0102) /* SD16 Channel 0 Control Register */
DEFW( SD16CCTL0 , SD16CCTL0_)
#define SD16CCTL1_ (0x0104) /* SD16 Channel 1 Control Register */
DEFW( SD16CCTL1 , SD16CCTL1_)
#define SD16CCTL2_ (0x0106) /* SD16 Channel 2 Control Register */
DEFW( SD16CCTL2 , SD16CCTL2_)
#define SD16IV_ (0x0110) /* SD16 Interrupt Vector Register */
DEFW( SD16IV , SD16IV_)
#define SD16MEM0_ (0x0112) /* SD16 Channel 0 Conversion Memory */
DEFW( SD16MEM0 , SD16MEM0_)
#define SD16MEM1_ (0x0114) /* SD16 Channel 1 Conversion Memory */
DEFW( SD16MEM1 , SD16MEM1_)
#define SD16MEM2_ (0x0116) /* SD16 Channel 2 Conversion Memory */
DEFW( SD16MEM2 , SD16MEM2_)
/* SD16INCTLx - AFEINCTLx */
#define SD16INCH0 (0x0001) /* SD16 Input Channel select 0 */
#define SD16INCH1 (0x0002) /* SD16 Input Channel select 1 */
#define SD16INCH2 (0x0004) /* SD16 Input Channel select 2 */
#define SD16GAIN0 (0x0008) /* SD16 Input Pre-Amplifier Gain Select 0 */
#define SD16GAIN1 (0x0010) /* SD16 Input Pre-Amplifier Gain Select 1 */
#define SD16GAIN2 (0x0020) /* SD16 Input Pre-Amplifier Gain Select 2 */
#define SD16INTDLY0 (0x0040) /* SD16 Interrupt Delay after 1.Conversion 0 */
#define SD16INTDLY1 (0x0080) /* SD16 Interrupt Delay after 1.Conversion 1 */
#define SD16GAIN_1 (0x0000) /* SD16 Input Pre-Amplifier Gain Select *1 */
#define SD16GAIN_2 (0x0008) /* SD16 Input Pre-Amplifier Gain Select *2 */
#define SD16GAIN_4 (0x0010) /* SD16 Input Pre-Amplifier Gain Select *4 */
#define SD16GAIN_8 (0x0018) /* SD16 Input Pre-Amplifier Gain Select *8 */
#define SD16GAIN_16 (0x0020) /* SD16 Input Pre-Amplifier Gain Select *16 */
#define SD16GAIN_32 (0x0028) /* SD16 Input Pre-Amplifier Gain Select *32 */
#define SD16INCH_0 (0x0000) /* SD16 Input Channel select input */
#define SD16INCH_1 (0x0001) /* SD16 Input Channel select input */
#define SD16INCH_2 (0x0002) /* SD16 Input Channel select input */
#define SD16INCH_3 (0x0003) /* SD16 Input Channel select input */
#define SD16INCH_4 (0x0004) /* SD16 Input Channel select input */
#define SD16INCH_5 (0x0005) /* SD16 Input Channel select input */
#define SD16INCH_6 (0x0006) /* SD16 Input Channel select Temp */
#define SD16INCH_7 (0x0007) /* SD16 Input Channel select Offset */
#define SD16INTDLY_0 (0x0000) /* SD16 Interrupt Delay: Int. after 4.Conversion */
#define SD16INTDLY_1 (0x0040) /* SD16 Interrupt Delay: Int. after 3.Conversion */
#define SD16INTDLY_2 (0x0080) /* SD16 Interrupt Delay: Int. after 2.Conversion */
#define SD16INTDLY_3 (0x00C0) /* SD16 Interrupt Delay: Int. after 1.Conversion */
/* SD16CTL - AFECTL */
#define SD16OVIE (0x0002) /* SD16 Overflow Interupt Enable */
#define SD16REFON (0x0004) /* SD16 Switch internal Reference on */
#define SD16VMIDON (0x0008) /* SD16 Switch Vmid Buffer on */
#define SD16SSEL0 (0x0010) /* SD16 Clock Source Select 0 */
#define SD16SSEL1 (0x0020) /* SD16 Clock Source Select 1 */
#define SD16DIV0 (0x0040) /* SD16 Clock Divider Select 0 */
#define SD16DIV1 (0x0080) /* SD16 Clock Divider Select 1 */
#define SD16LP (0x0100) /* SD16 Low Power Mode Enable */
#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */
#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0+SD16DIV1) /* SD16 Clock Divider Select /8 */
#define SD16SSEL_0 (0x0000) /* SD16 Clock Source Select MCLK */
#define SD16SSEL_1 (SD16SSEL0) /* SD16 Clock Source Select SMCLK */
#define SD16SSEL_2 (SD16SSEL1) /* SD16 Clock Source Select ACLK */
#define SD16SSEL_3 (SD16SSEL0+SD16SSEL1) /* SD16 Clock Source Select TACLK */
/* SD16CCTLx - AFECCTLx */
#define SD16GRP (0x0001) /* SD16 Grouping of Channels: 0:Off/1:On */
#define SD16SC (0x0002) /* SD16 Start Conversion */
#define SD16IFG (0x0004) /* SD16 Channel x Interrupt Flag */
#define SD16IE (0x0008) /* SD16 Channel x Interrupt Enable */
#define SD16DF (0x0010) /* SD16 Channel x Data Format: 0:Unipolar/1:Bipolar */
#define SD16OVIFG (0x0020) /* SD16 Channel x Overflow Interrupt Flag */
#define SD16LSBACC (0x0040) /* SD16 Channel x Access LSB of ADC */
#define SD16LSBTOG (0x0080) /* SD16 Channel x Toggle LSB Output of ADC */
#define SD16OSR0 (0x0100) /* SD16 Channel x OverSampling Ratio 0 */
#define SD16OSR1 (0x0200) /* SD16 Channel x OverSampling Ratio 1 */
#define SD16SNGL (0x0400) /* SD16 Channel x Single Conversion On/Off */
#define SD16OSR_256 (0x0000) /* SD16 Channel x OverSampling Ratio 256 */
#define SD16OSR_128 (0x0100) /* SD16 Channel x OverSampling Ratio 128 */
#define SD16OSR_64 (0x0200) /* SD16 Channel x OverSampling Ratio 64 */
#define SD16OSR_32 (0x0300) /* SD16 Channel x OverSampling Ratio 32 */
/************************************************************
* ESP430E
************************************************************/
#define __MSP430_HAS_ESP430E__ /* Definition to show that Module is available */
#define AFEINCTL0 SD16INCTL0 /* AFE Input Control Register Channel 0 */
#define AFEINCTL1 SD16INCTL1 /* AFE Input Control Register Channel 1 */
#define AFEINCTL2 SD16INCTL2 /* AFE Input Control Register Channel 2 */
#define AFECTL SD16CTL /* Analog Front End Control Register */
#define AFECCTL0 SD16CCTL0 /* AFE Channel 0 Control Register */
#define AFECCTL1 SD16CCTL1 /* AFE Channel 1 Control Register */
#define AFECCTL2 SD16CCTL2 /* AFE Channel 2 Control Register */
#define ESPCTL_ (0x0150) /* ESP430 Control Register */
DEFW( ESPCTL , ESPCTL_)
#define MBCTL_ (0x0152) /* Mailbox Control Register */
DEFW( MBCTL , MBCTL_)
#define MBIN0_ (0x0154) /* Incoming Mailbox 0 Register */
DEFW( MBIN0 , MBIN0_)
#define MBIN1_ (0x0156) /* Incoming Mailbox 1 Register */
DEFW( MBIN1 , MBIN1_)
#define MBOUT0_ (0x0158) /* Outgoing Mailbox 0 Register */
DEFW( MBOUT0 , MBOUT0_)
#define MBOUT1_ (0x015A) /* Outgoing Mailbox 1 Register */
DEFW( MBOUT1 , MBOUT1_)
#define ESP430_STAT0_ (0x01C0) /* ESP430 Return Value 0 */
READ_ONLY DEFW( ESP430_STAT0 , ESP430_STAT0_)
#define ESP430_STAT1_ (0x01C2) /* ESP430 Return Value 1 */
READ_ONLY DEFW( ESP430_STAT1 , ESP430_STAT1_)
#define WAVEFSV1_ (0x01C4) /* ESP430 Return Value 2 */
READ_ONLY DEFW( WAVEFSV1 , WAVEFSV1_)
#define RET3_ (0x01C6) /* ESP430 Return Value 3 */
READ_ONLY DEFW( RET3 , RET3_)
#define RET4_ (0x01C8) /* ESP430 Return Value 4 */
READ_ONLY DEFW( RET4 , RET4_)
#define WAVEFSI1_ (0x01CA) /* ESP430 Return Value 5 */
READ_ONLY DEFW( WAVEFSI1 , WAVEFSI1_)
#define WAVEFSI2_ (0x01CC) /* ESP430 Return Value 6 */
READ_ONLY DEFW( WAVEFSI2 , WAVEFSI2_)
#define RET7_ (0x01CE) /* ESP430 Return Value 7 */
READ_ONLY DEFW( RET7 , RET7_)
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