📄 msp430xe42x.h
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#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */
#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */
#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */
#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
#define LCDMEM_ (0x0091) /* LCD Memory */
#ifndef __IAR_SYSTEMS_ICC
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
#endif
#define LCDM1_ (0x0091) /* LCD Memory 1 */
DEFC( LCDM1 , LCDM1_)
#define LCDM2_ (0x0092) /* LCD Memory 2 */
DEFC( LCDM2 , LCDM2_)
#define LCDM3_ (0x0093) /* LCD Memory 3 */
DEFC( LCDM3 , LCDM3_)
#define LCDM4_ (0x0094) /* LCD Memory 4 */
DEFC( LCDM4 , LCDM4_)
#define LCDM5_ (0x0095) /* LCD Memory 5 */
DEFC( LCDM5 , LCDM5_)
#define LCDM6_ (0x0096) /* LCD Memory 6 */
DEFC( LCDM6 , LCDM6_)
#define LCDM7_ (0x0097) /* LCD Memory 7 */
DEFC( LCDM7 , LCDM7_)
#define LCDM8_ (0x0098) /* LCD Memory 8 */
DEFC( LCDM8 , LCDM8_)
#define LCDM9_ (0x0099) /* LCD Memory 9 */
DEFC( LCDM9 , LCDM9_)
#define LCDM10_ (0x009A) /* LCD Memory 10 */
DEFC( LCDM10 , LCDM10_)
#define LCDM11_ (0x009B) /* LCD Memory 11 */
DEFC( LCDM11 , LCDM11_)
#define LCDM12_ (0x009C) /* LCD Memory 12 */
DEFC( LCDM12 , LCDM12_)
#define LCDM13_ (0x009D) /* LCD Memory 13 */
DEFC( LCDM13 , LCDM13_)
#define LCDM14_ (0x009E) /* LCD Memory 14 */
DEFC( LCDM14 , LCDM14_)
#define LCDM15_ (0x009F) /* LCD Memory 15 */
DEFC( LCDM15 , LCDM15_)
#define LCDM16_ (0x00A0) /* LCD Memory 16 */
DEFC( LCDM16 , LCDM16_)
#define LCDM17_ (0x00A1) /* LCD Memory 17 */
DEFC( LCDM17 , LCDM17_)
#define LCDM18_ (0x00A2) /* LCD Memory 18 */
DEFC( LCDM18 , LCDM18_)
#define LCDM19_ (0x00A3) /* LCD Memory 19 */
DEFC( LCDM19 , LCDM19_)
#define LCDM20_ (0x00A4) /* LCD Memory 20 */
DEFC( LCDM20 , LCDM20_)
#define LCDMA (LCDM10) /* LCD Memory A */
#define LCDMB (LCDM11) /* LCD Memory B */
#define LCDMC (LCDM12) /* LCD Memory C */
#define LCDMD (LCDM13) /* LCD Memory D */
#define LCDME (LCDM14) /* LCD Memory E */
#define LCDMF (LCDM15) /* LCD Memory F */
/************************************************************
* USART
************************************************************/
/* UxCTL */
#define PENA (0x80) /* Parity enable */
#define PEV (0x40) /* Parity 0:odd / 1:even */
#define SPB (0x20) /* Stop Bits 0:one / 1: two */
#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */
#define LISTEN (0x08) /* Listen mode */
#define SYNC (0x04) /* UART / SPI mode */
#define MM (0x02) /* Master Mode off/on */
#define SWRST (0x01) /* USART Software Reset */
/* UxTCTL */
#define CKPH (0x80) /* SPI: Clock Phase */
#define CKPL (0x40) /* Clock Polarity */
#define SSEL1 (0x20) /* Clock Source Select 1 */
#define SSEL0 (0x10) /* Clock Source Select 0 */
#define URXSE (0x08) /* Receive Start edge select */
#define TXWAKE (0x04) /* TX Wake up mode */
#define STC (0x02) /* SPI: STC enable 0:on / 1:off */
#define TXEPT (0x01) /* TX Buffer empty */
/* UxRCTL */
#define FE (0x80) /* Frame Error */
#define PE (0x40) /* Parity Error */
#define OE (0x20) /* Overrun Error */
#define BRK (0x10) /* Break detected */
#define URXEIE (0x08) /* RX Error interrupt enable */
#define URXWIE (0x04) /* RX Wake up interrupt enable */
#define RXWAKE (0x02) /* RX Wake up detect */
#define RXERR (0x01) /* RX Error Error */
/************************************************************
* USART 0
************************************************************/
#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */
#define U0CTL_ (0x0070) /* USART 0 Control */
DEFC( U0CTL , U0CTL_)
#define U0TCTL_ (0x0071) /* USART 0 Transmit Control */
DEFC( U0TCTL , U0TCTL_)
#define U0RCTL_ (0x0072) /* USART 0 Receive Control */
DEFC( U0RCTL , U0RCTL_)
#define U0MCTL_ (0x0073) /* USART 0 Modulation Control */
DEFC( U0MCTL , U0MCTL_)
#define U0BR0_ (0x0074) /* USART 0 Baud Rate 0 */
DEFC( U0BR0 , U0BR0_)
#define U0BR1_ (0x0075) /* USART 0 Baud Rate 1 */
DEFC( U0BR1 , U0BR1_)
#define U0RXBUF_ (0x0076) /* USART 0 Receive Buffer */
READ_ONLY DEFC( U0RXBUF , U0RXBUF_)
#define U0TXBUF_ (0x0077) /* USART 0 Transmit Buffer */
DEFC( U0TXBUF , U0TXBUF_)
/* Alternate register names */
#define UCTL0 U0CTL /* USART 0 Control */
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
#define URCTL0 U0RCTL /* USART 0 Receive Control */
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL0_ U0CTL_ /* USART 0 Control */
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
#define UCTL_0 U0CTL /* USART 0 Control */
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0_ U0CTL_ /* USART 0 Control */
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
/************************************************************
* Timer A3
************************************************************/
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input divider 1 */
#define ID0 (0x0040) /* Timer A clock input divider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
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