_primary.vhd

来自「arm7的IP软核代码」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity InterruptPriority is
    port(
        Fiq             : in     vl_logic;
        Irq             : in     vl_logic;
        FiqDisable      : in     vl_logic;
        IrqDisable      : in     vl_logic;
        TrueFiq         : out    vl_logic;
        TrueIrq         : out    vl_logic
    );
end InterruptPriority;