_primary.vhd

arm7的IP软核代码

library verilog;
use verilog.vl_types.all;
entity WishBone_Arbiter is
    port(
        wb_cyc_1        : in     vl_logic;
        wb_cyc_2        : in     vl_logic;
        wb_gnt_1        : out    vl_logic;
        wb_gnt_2        : out    vl_logic;
        clk_i           : in     vl_logic;
        rst_i           : in     vl_logic
    );
end WishBone_Arbiter;