_primary.vhd

来自「arm7的IP软核代码」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity thumb_2_nnarm is
    port(
        in_AddressGoWithInstruction: in     vl_logic_vector(31 downto 0);
        cti             : in     vl_logic_vector(15 downto 0);
        reset           : in     vl_logic;
        clock           : in     vl_logic;
        out_ClearBit1   : out    vl_logic;
        out_AddressOfFirstHalf: out    vl_logic_vector(31 downto 0);
        arm_inst        : out    vl_logic_vector(31 downto 0);
        in_ChangePC     : in     vl_logic;
        in_MEMChangePC  : in     vl_logic
    );
end thumb_2_nnarm;