_primary.vhd

arm7的IP软核代码

library verilog;
use verilog.vl_types.all;
entity \IF\ is
    port(
        in_Instruction  : in     vl_logic_vector(31 downto 0);
        in_InstructionWait: in     vl_logic;
        out_InstructionAddress: out    vl_logic_vector(31 downto 0);
        out_FourthReadRegisterEnable: out    vl_logic;
        out_FourthReadRegisterNumber: out    vl_logic_vector(7 downto 0);
        in_FourthReadBus: in     vl_logic_vector(31 downto 0);
        out_SecondWriteRegisterEnable: out    vl_logic;
        out_SecondWriteRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_SecondWriteBus: out    vl_logic_vector(31 downto 0);
        in_IDCanGo      : in     vl_logic;
        out_Instruction : out    vl_logic_vector(31 downto 0);
        out_ValidInstruction: out    vl_logic;
        out_AddressGoWithInstruction: out    vl_logic_vector(31 downto 0);
        out_NextInstructionAddress: out    vl_logic_vector(31 downto 0);
        in_ChangePC     : in     vl_logic;
        in_NewPC        : in     vl_logic_vector(31 downto 0);
        in_MEMChangePC  : in     vl_logic;
        in_MEMNewPC     : in     vl_logic_vector(31 downto 0);
        in_ThumbState   : in     vl_logic;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end \IF\;