_primary.vhd

arm7的IP软核代码

library verilog;
use verilog.vl_types.all;
entity Decoder_ARM is
    port(
        in_ValidInstruction_IFID: in     vl_logic;
        in_PipelineRegister_IFID: in     vl_logic_vector(31 downto 0);
        in_AddressGoWithInstruction: in     vl_logic_vector(31 downto 0);
        in_NextInstructionAddress: in     vl_logic_vector(31 downto 0);
        out_IDOwnCanGo  : out    vl_logic;
        out_LeftReadRegisterEnable: out    vl_logic;
        out_LeftReadRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_RightReadRegisterEnable: out    vl_logic;
        out_RightReadRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_ThirdReadRegisterEnable: out    vl_logic;
        out_ThirdReadRegisterNumber: out    vl_logic_vector(7 downto 0);
        out_ALUEnable   : out    vl_logic;
        out_ALUType     : out    vl_logic_vector(7 downto 0);
        out_ALULeftRegister: out    vl_logic_vector(7 downto 0);
        out_ALURightRegister: out    vl_logic_vector(7 downto 0);
        out_ALUThirdRegister: out    vl_logic_vector(7 downto 0);
        out_ALULeftFromImm: out    vl_logic;
        out_ALURightFromImm: out    vl_logic;
        out_ALUThirdFromImm: out    vl_logic;
        out_CPSRFromImm : out    vl_logic;
        out_SPSRFromImm : out    vl_logic;
        out_ALUTargetRegister: out    vl_logic_vector(7 downto 0);
        out_ALUExtendedImmediateValue: out    vl_logic_vector(31 downto 0);
        out_ALURightShiftType: out    vl_logic_vector(1 downto 0);
        out_ALUSecondImmediateValue: out    vl_logic_vector(31 downto 0);
        out_SimpleALUType: out    vl_logic_vector(7 downto 0);
        out_SimpleALUTargetRegister: out    vl_logic_vector(7 downto 0);
        out_ALUMisc     : out    vl_logic_vector(31 downto 0);
        out_ALUPSRType  : out    vl_logic_vector(7 downto 0);
        out_AddressGoWithInstruction2ALU: out    vl_logic_vector(31 downto 0);
        out_NextAddressGoWithInstruction2ALU: out    vl_logic_vector(31 downto 0);
        out_MEMEnable   : out    vl_logic;
        out_MEMType     : out    vl_logic_vector(7 downto 0);
        out_MEMTargetRegister: out    vl_logic_vector(7 downto 0);
        out_SimpleMEMType: out    vl_logic_vector(7 downto 0);
        out_SimpleMEMTargetRegister: out    vl_logic_vector(7 downto 0);
        out_MEMPSRType  : out    vl_logic_vector(7 downto 0);
        in_ThumbState   : in     vl_logic;
        in_IsInPrivilegedMode: in     vl_logic;
        in_TrueFiq      : in     vl_logic;
        in_TrueIrq      : in     vl_logic;
        in_ALUCanGo     : in     vl_logic;
        in_ChangePC     : in     vl_logic;
        in_MEMChangePC  : in     vl_logic;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end Decoder_ARM;