📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity MemoryController_WB_Bhv is port( clk_i : in vl_logic; rst_i : in vl_logic; wb_addr_i : in vl_logic_vector(31 downto 0); wb_data_i : in vl_logic_vector(31 downto 0); wb_data_o : out vl_logic_vector(31 downto 0); wb_sel_i : in vl_logic_vector(7 downto 0); wb_we_i : in vl_logic; wb_cyc_i : in vl_logic; wb_stb_i : in vl_logic; wb_ack_o : out vl_logic; wb_err_o : out vl_logic );end MemoryController_WB_Bhv;
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