_primary.vhd

arm7的IP软核代码

library verilog;
use verilog.vl_types.all;
entity StatusRegisters is
    port(
        in_IfChangeState: in     vl_logic;
        in_ChangeStateAction: in     vl_logic_vector(4 downto 0);
        in_CPSRWriteEnable: in     vl_logic;
        in_CPSRWriteValue: in     vl_logic_vector(31 downto 0);
        in_SPSRWriteEnable: in     vl_logic;
        in_SPSRWriteValue: in     vl_logic_vector(31 downto 0);
        out_CPSR        : out    vl_logic_vector(31 downto 0);
        out_SPSR        : out    vl_logic_vector(31 downto 0);
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end StatusRegisters;