_primary.vhd

arm7的IP软核代码

library verilog;
use verilog.vl_types.all;
entity nnARMCore is
    port(
        \Wait\          : in     vl_logic;
        Instruction     : in     vl_logic_vector(31 downto 0);
        out_InstructionAddress: out    vl_logic_vector(31 downto 0);
        out_MEMAccessAddress: out    vl_logic_vector(31 downto 0);
        DataBus_r       : in     vl_logic_vector(31 downto 0);
        DataBus_f       : out    vl_logic_vector(31 downto 0);
        out_MEMAccessRequest: out    vl_logic;
        out_MEMAccessBW : out    vl_logic;
        out_MEMAccessRW : out    vl_logic;
        out_DataCacheWait: in     vl_logic;
        Fiq             : in     vl_logic;
        Irq             : in     vl_logic;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end nnARMCore;