_primary.vhd

来自「arm7的IP软核代码」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity complementary is
    port(
        out_Result      : out    vl_logic_vector(31 downto 0);
        in_Operand      : in     vl_logic_vector(31 downto 0)
    );
end complementary;