_primary.vhd

来自「arm7的IP软核代码」· VHDL 代码 · 共 34 行

library verilog;
use verilog.vl_types.all;
entity RegisterFile is
    port(
        in_IfChangeState: in     vl_logic;
        in_MemAccessUserBankRegister2WB: in     vl_logic;
        in_ChangeStateAction: in     vl_logic_vector(4 downto 0);
        in_LeftReadEnable: in     vl_logic;
        in_LeftReadRegisterNumber: in     vl_logic_vector(7 downto 0);
        out_LeftReadBus : out    vl_logic_vector(31 downto 0);
        in_RightReadEnable: in     vl_logic;
        in_RightReadRegisterNumber: in     vl_logic_vector(7 downto 0);
        out_RightReadBus: out    vl_logic_vector(31 downto 0);
        in_ThirdReadEnable: in     vl_logic;
        in_ThirdReadRegisterNumber: in     vl_logic_vector(7 downto 0);
        out_ThirdReadBus: out    vl_logic_vector(31 downto 0);
        in_FourthReadEnable: in     vl_logic;
        in_FourthReadRegisterNumber: in     vl_logic_vector(7 downto 0);
        out_FourthReadBus: out    vl_logic_vector(31 downto 0);
        in_WriteEnable  : in     vl_logic;
        in_WriteRegisterNumber: in     vl_logic_vector(7 downto 0);
        in_WriteBus     : in     vl_logic_vector(31 downto 0);
        in_SecondWriteEnable: in     vl_logic;
        in_SecondWriteRegisterNumber: in     vl_logic_vector(7 downto 0);
        in_SecondWriteBus: in     vl_logic_vector(31 downto 0);
        in_ThirdWriteEnable: in     vl_logic;
        in_ThirdWriteRegisterNumber: in     vl_logic_vector(7 downto 0);
        in_ThirdWriteBus: in     vl_logic_vector(31 downto 0);
        in_ProcessorMode: in     vl_logic_vector(4 downto 0);
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end RegisterFile;