📄 mtv230.lst
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C51 COMPILER V7.50 MTV230 07/11/2005 15:03:05 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE MTV230
OBJECT MODULE PLACED IN mtv230.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE mtv230.c BROWSE DEBUG OBJECTEXTEND
line level source
1 /***********************************************************************
2 * Project: MTV230+CS7110+UPS017
3 *
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4 * File: Mtv230.c (Source)
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5 *
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6 * Version: V1.0
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7 *
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8 * Created: 2004.11.2
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9 * Last Change: 2005.7.11
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10 *
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11 * Author: Yuan K
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12 *
13 * Company: MYSON
14 *
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15 * Compiler: KEIL C51 V7.04
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16 *
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17 * Description:
18 *
19 * MTV230(@12MHz)
20 *
21 *Copyright (c) Century Integration Technology, Inc.
22 *All rights reserved.
23 *
24 ***********************************************************************/
25
26 #include "Globe.h"
27
28 BYTE xdata byM230_PadMode1 _at_ 0xF2B; // HIICE IIICE HVE HclpE - - FclkE P62E
29 BYTE xdata byM230_PadMode2 _at_ 0xF2C; // DA3E DA2E DA1E DA0E AD3E AD2E AD1E AD0E
30 BYTE xdata byM230_PadMode3 _at_ 0xF2D; // P47oe P46oe P45oe P44oe P43oe P42oe P41oe P40oe
31 BYTE xdata byM230_PadMode4 _at_ 0xF2E; // P57oe P56oe P55oe P54oe P53oe P52oe P51oe P50oe
32 BYTE xdata byM230_Option1 _at_ 0xF2F; // PWMF DIV253 SlvAbs1 SlvAbs0 ENSCL Msel MIICF1 MIICF0
33 //I/O ports
34 BYTE xdata byM230_Port40 _at_ 0xF30;
35 BYTE xdata byM230_Port41 _at_ 0xF31;
36 BYTE xdata byM230_Port42 _at_ 0xF32;
37 BYTE xdata byM230_Port43 _at_ 0xF33;
38 BYTE xdata byM230_Port44 _at_ 0xF34;
39 BYTE xdata byM230_Port45 _at_ 0xF35;
40 BYTE xdata byM230_Port46 _at_ 0xF36;
41 BYTE xdata byM230_Port47 _at_ 0xF37;
42
43 BYTE xdata byM230_Port50 _at_ 0xF38;
C51 COMPILER V7.50 MTV230 07/11/2005 15:03:05 PAGE 2
44 BYTE xdata byM230_Port51 _at_ 0xF39;
45 BYTE xdata byM230_Port52 _at_ 0xF3A;
46 BYTE xdata byM230_Port53 _at_ 0xF3B;
47 BYTE xdata byM230_Port54 _at_ 0xF3C;
48 BYTE xdata byM230_Port55 _at_ 0xF3D;
49 BYTE xdata byM230_Port56 _at_ 0xF3E;
50 BYTE xdata byM230_Port57 _at_ 0xF3F;
51 BYTE xdata byM230_Port60 _at_ 0xF28;
52 BYTE xdata byM230_Port61 _at_ 0xF29;
53 BYTE xdata byM230_Port62 _at_ 0xF2A;
54 // define MTV230M's PWM DAC register
55 BYTE xdata byM230_DA0 _at_ 0xF20; // pulse width of PWM DAC0
56 BYTE xdata byM230_DA1 _at_ 0xF21;
57 BYTE xdata byM230_DA2 _at_ 0xF22;
58 BYTE xdata byM230_DA3 _at_ 0xF23;
59 //define MTV230M's H/V Sync processor register
60 BYTE xdata byM230_HVSTUS _at_ 0xF40; // CVpre - Hpol Vpol Hpre Vpre Hiff Voff
61 #define byM230_HVCTR0 byM230_HVSTUS
62 //BYTE xdata byM230_HVCTR0 _at_ 0xF40;
63 BYTE xdata byM230_HCNTH _at_ 0xF41; // Hovf - HF13 HF12 HF11 HF10 HF9 HF8
64 BYTE xdata byM230_HCNTL _at_ 0xF42; // HF7 HF6 HF5 HF4 HF3 HF2 HF1 HF0
65 BYTE xdata byM230_VCNTH _at_ 0xF43; // Vvof - - - VF11 VF10 VF9 VF8
66 //#define byM230_HVCTR3 byM230_VCNTH
67 BYTE xdata byM230_VCNTL _at_ 0xF44; // VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0
68 //#define byM230_HVCTR4 byM230_VCNTL
69 BYTE xdata byM230_INTFLG _at_ 0xF48; // HPRchg VPRchg HPLchg VPLchg HFchg VFchg - Vsync
70 BYTE xdata byM230_INTEN _at_ 0xF49; // EHPR EVPR EHPL EVPL EHF EVF - EVsync
71 //define MTV230's DDC&IIC's control
72 BYTE xdata byM230_IIC_CTR _at_ 0xF00; // IIC interface control
73 BYTE xdata byM230_IIC_STUS1 _at_ 0xF01; // IIC interface status
74 BYTE xdata byM230_IIC_STUS2 _at_ 0xF02;
75 BYTE xdata byM230_IIC_INTFLG _at_ 0xF03; // interrupt flag
76 BYTE xdata byM230_IIC_INTEN _at_ 0xF04; // interrupt enable
77 BYTE xdata byM230_IIC_MBUF _at_ 0xF05; // master IIC data shiftregister
78 BYTE xdata byM230_IIC_TXRCABUF _at_ 0xF06; // slave A IIC receive/transmit buffer
79 BYTE xdata byM230_IIC_SLVAADR _at_ 0xF07; // ENSlvA slave A IIC address
80 BYTE xdata byM230_IIC_TXRCBBUF _at_ 0xF08; // slave B IIC receive/transmit buffer
81 BYTE xdata byM230_IIC_SLVBADR _at_ 0xF09; // ENSlvB slave B IIC address
82 //BYTE xdata byM230_IIC_DBUF _at_ 0xF0A;
83 // ISP
84 BYTE xdata byM230_ISPSLV _at_ 0xF0B; // ISP slave address
85 BYTE xdata byM230_ISPEN _at_ 0xF0C; // write 0x93H to enable ISP mode
86 //define MTV230's A/D converter
87 BYTE xdata byM230_WDT _at_ 0xF18; // WEN WCLR - - - WDT2 WDT1 WDT0
88 //define OSD register
89 BYTE xdata byM230_OSDRA _at_ 0xFA0;
90 BYTE xdata byM230_OSDCA _at_ 0xFA1;
91 BYTE xdata byM230_OSDDT0 _at_ 0xFA2;
92 BYTE xdata byM230_OSDDT1 _at_ 0xFA3;
93 //BYTE xdata byM230_WinReg[12] _at_ 0xFC0;
94 BYTE xdata byM230_W1ROW _at_ 0xFC0;
95 BYTE xdata byM230_W1COL1 _at_ 0xFC1;
96 BYTE xdata byM230_W1COL2 _at_ 0xFC2;
97 BYTE xdata byM230_W2ROW _at_ 0xFC3;
98 BYTE xdata byM230_W2COL1 _at_ 0xFC4;
99 BYTE xdata byM230_W2COL2 _at_ 0xFC5;
100 BYTE xdata byM230_W3ROW _at_ 0xFC6;
101 BYTE xdata byM230_W3COL1 _at_ 0xFC7;
102 BYTE xdata byM230_W3COL2 _at_ 0xFC8;
103 BYTE xdata byM230_W4ROW _at_ 0xFC9;
104 BYTE xdata byM230_W4COL1 _at_ 0xFCA;
105 BYTE xdata byM230_W4COL2 _at_ 0xFCB;
C51 COMPILER V7.50 MTV230 07/11/2005 15:03:05 PAGE 3
106 BYTE xdata byM230_VERTD _at_ 0xFCC;
107 BYTE xdata byM230_HORD _at_ 0xFCD;
108 BYTE xdata byM230_CH _at_ 0xFCE;
109 BYTE xdata byM230_RSPACE _at_ 0xFD0;
110 BYTE xdata byM230_OSDCON _at_ 0xFD1;
111 BYTE xdata byM230_OSDCON1 _at_ 0xFD2;
112 BYTE xdata byM230_CHSC _at_ 0xFD3;
113 BYTE xdata byM230_FSSTP _at_ 0xFD4;
114 BYTE xdata byM230_WINSW _at_ 0xFD5;
115 BYTE xdata byM230_WINSH _at_ 0xFD6;
116 BYTE xdata byM230_WINSC _at_ 0xFD7;
117 BYTE xdata byM230_WINSC1 _at_ 0xFD8;
118 BYTE xdata byM230_XDEL _at_ 0xFD9;
119
120 void initial_MTV230(void)
121 {
122 1
123 1 POWER_STANDBY = 0;
124 1
125 1 byM230_Option1 = 0x80; //master IIC block connect to HSCL/HSDA pins
126 1 byM230_PadMode1 = 0xc1; //bit7 HIICE=1: HSCL/HSDA
127 1 //bit6 IIICE=1: ISCL/ISDA
128 1 //bit5 HVE=0: P4.7
129 1 //bit4 HclpE=0: P4.5
130 1 //bit1 FclkE=0: CPU at normal rate
131 1 //bit0 P62E=1: P6.2
132 1 byM230_PadMode2 = 0xf0; //enable DA0~DA3
133 1 byM230_PadMode3 = 0xFC; //p4.1=ISP VSYNC, P4.0=HSYNC
134 1 byM230_PadMode4 = 0xff; // P5.1~~P5.7 are output pins
135 1
136 1
137 1 byM230_IIC_INTEN = 0xe0; /////enable TXBBUF RCBBUF slave B interrupt
138 1 byM230_IIC_SLVBADR = 0x80|(0xC6>>1); //C6=Address(7 bit) + WR bit
139 1
140 1 byM230_HVCTR0 = 0xc3; ////////MTV 230 datasheet PAGE11
141 1 byM230_WDT= 0x00; //disable watchdog
142 1 byM230_INTFLG = 0x00; //clear HSYNC VSYNC's change flags and VSYNC interrupt flag
143 1 byM230_INTEN = 0x00; //disable the interrupt about HSYNC and VSYNC
144 1
145 1 byM230_IIC_INTFLG = 0; //clear SlvBMI SlvAMI and Master IIC interrupt flag
146 1 byM230_IIC_SLVAADR = 0x50; // disable slaveA,address:- 1 0 1 0 0 0 0
147 1 // byM230_IIC_SLVBADR = 0x80|(0xc6>>1); // disable slaveB,address:- 0 1 0 0 1 1 0
148 1 // byM230_IIC_INTEN = 0xe1; // enable master
149 1
150 1 //byM230_OSDCON1=0x0c;
151 1 //PowerCtrl = 1; //power on control pin
152 1 //POWER_STANDBY = 1; //power on flag
153 1 }
154
155 void initial_MCU(void)
156 {
157 1 EA = 0; //disable all interrupt
158 1
159 1 SCON=0;
160 1 TMOD = 0x21; // 16 bit timer/counter
161 1 IT1 = 0; // set INT1 type=falling edge
162 1 //IT1 = 1; // set INT1 type=falling edge
163 1 IE1 = 0; // extern interrupt 1 flag
164 1 EX1 = 1; // enable INT1
165 1
166 1 EX0 = 1;
167 1 IT0 = 1;
C51 COMPILER V7.50 MTV230 07/11/2005 15:03:05 PAGE 4
168 1 ET0 = 1; // enable TIMER0
169 1 ES = 0;
170 1 PX1 = 1; // INT1 priority high
171 1 PT0 = 0; // set TIMER0 priority low
172 1
173 1 TH0 = HiByte(65536-TIME_BASE1*1000); //set next interrupt time TIME_BASE1 ms
174 1 TL0 = LoByte(65536-TIME_BASE1*1000);
175 1
176 1 TR0 = 1; // start timer
177 1 EA = 1; // enable all interrupt
178 1
179 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 103 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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