alu.tan.summary

来自「用VERILOG实现ALU」· SUMMARY 代码 · 共 47 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 70.321 ns
From           : a[7]
To             : out[7]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.423 ns
From           : out[0]~reg0
To             : out[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.550 ns
From           : b[6]
To             : out[6]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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