alu.fit.summary

来自「用VERILOG实现ALU」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Sat Mar 15 10:29:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : alu
Top-level Entity Name : alu
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 11 %
    Combinational ALUTs : 1,328 / 12,480 ( 11 % )
    Dedicated logic registers : 8 / 12,480 ( < 1 % )
Total registers : 8
Total pins : 46 / 343 ( 13 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )