alu.map.rpt

用VERILOG实现ALU

;                                               ;       ;
; Total combinational functions                 ; 1327  ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 8     ;
;     -- 6 input functions                      ; 228   ;
;     -- 5 input functions                      ; 713   ;
;     -- 4 input functions                      ; 332   ;
;     -- <=3 input functions                    ; 46    ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 1319  ;
;     -- extended LUT mode                      ; 8     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 1871  ;
;                                               ;       ;
; Total registers                               ; 8     ;
;     -- Dedicated logic registers              ; 8     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 936   ;
;                                               ;       ;
; I/O pins                                      ; 46    ;
; Maximum fan-out node                          ; g[7]  ;
; Maximum fan-out                               ; 293   ;
; Total fan-out                                 ; 6463  ;
; Average fan-out                               ; 4.68  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |alu                       ; 1327 (1327)       ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 46   ; 0            ; |alu                ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 8 bits    ; 24 ALUTs      ; 24 ALUTs             ; 0 ALUTs                ; Yes        ; |alu|out[6]~reg0           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |alu ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; m              ; 8     ; Signed Integer                             ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Mar 15 10:28:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu
Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for "a" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(5): "a" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for "b" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(5): "b" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for "g" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(5): "g" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for "n" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(6): "n" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for "ALUFN" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(7): "ALUFN" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(8): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(9): "out" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for "a" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(43): "a" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for "b" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(43): "b" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for "g" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(43): "g" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(44): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(45): "out" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(75): data type declaration for "a" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(76): "a" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(75): data type declaration for "g" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(76): "g" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(75): data type declaration for "n" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(77): "n" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(78): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(79): "out" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for "a" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(120): "a" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for "b" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(120): "b" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for "g" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(120): "g" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(121): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(122): "out" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for "a" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(177): "a" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for "b" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(177): "b" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for "g" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(177): "g" is declared here
Warning (10227): Verilog HDL Port Declaration warning at alu.v(178): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at alu.v(179): "out" is declared here
Info: Found 1 design units, including 1 entities, in source file alu.v
    Info: Found entity 1: alu
Info: Elaborating entity "alu" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at alu.v(84): truncated value with size 9 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at alu.v(49): truncated value with size 9 to match size of target (8)
Warning: Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "a[8]"
    Warning (15610): No output dependent on input pin "b[8]"
    Warning (15610): No output dependent on input pin "g[8]"
Info: Implemented 1373 device resources after synthesis - the final resource count might be different
    Info: Implemented 38 input pins
    Info: Implemented 8 output pins
    Info: Implemented 1327 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
    Info: Allocated 149 megabytes of memory during processing
    Info: Processing ended: Sat Mar 15 10:29:21 2008
    Info: Elapsed time: 00:00:50