pc.v.bak

来自「用VERILOG实现ALU」· BAK 代码 · 共 22 行

module pc(clk,reset,ia)
input clk,reset;
output ia;
reg [4:0] ia;
 
always @(reset)  //difference between DFF and D-latch
  begin
  if(reset==0)
     ia<=4'b00000;
   wait(reset!=0);
  end
  

always @(posedge clk)
  if(ia==4'b11111)
     ia<=4'b00000;
  else 
    ia<=ia+1;

endmodule