prev_cmp_alu.qmsg

用VERILOG实现ALU

{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(119) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 119 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(119) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 119 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(121) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(121): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 121 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(122) " "Info (10151): Verilog HDL Declaration information at alu.v(122): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 122 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(178) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(178): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 178 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(179) " "Info (10151): Verilog HDL Declaration information at alu.v(179): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 179 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}