alu.map.qmsg

来自「用VERILOG实现ALU」· QMSG 代码 · 共 49 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 15 10:48:15 2008 " "Info: Processing started: Sat Mar 15 10:48:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(5) " "Info (10151): Verilog HDL Declaration information at alu.v(5): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 5 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(5) " "Info (10151): Verilog HDL Declaration information at alu.v(5): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 5 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(5) " "Info (10151): Verilog HDL Declaration information at alu.v(5): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 5 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "n packed alu.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for \"n\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "n alu.v(6) " "Info (10151): Verilog HDL Declaration information at alu.v(6): \"n\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 6 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "ALUFN packed alu.v(4) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(4): data type declaration for \"ALUFN\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "ALUFN alu.v(7) " "Info (10151): Verilog HDL Declaration information at alu.v(7): \"ALUFN\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 7 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(8) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(8): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 8 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(9) " "Info (10151): Verilog HDL Declaration information at alu.v(9): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 9 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(42) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 42 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(43) " "Info (10151): Verilog HDL Declaration information at alu.v(43): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 43 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(42) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 42 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(43) " "Info (10151): Verilog HDL Declaration information at alu.v(43): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 43 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(42) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(42): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 42 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(43) " "Info (10151): Verilog HDL Declaration information at alu.v(43): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 43 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(44) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(44): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 44 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(45) " "Info (10151): Verilog HDL Declaration information at alu.v(45): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 45 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(75) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(75): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 75 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(76) " "Info (10151): Verilog HDL Declaration information at alu.v(76): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 76 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}