prev_cmp_alu.map.qmsg

用VERILOG实现ALU

{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "n alu.v(77) " "Info (10151): Verilog HDL Declaration information at alu.v(77): \"n\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 77 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(78) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(78): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 78 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(79) " "Info (10151): Verilog HDL Declaration information at alu.v(79): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 79 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(119) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 119 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(119) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 119 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(119) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(119): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 119 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(120) " "Info (10151): Verilog HDL Declaration information at alu.v(120): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 120 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(121) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(121): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 121 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(122) " "Info (10151): Verilog HDL Declaration information at alu.v(122): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 122 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "a packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"a\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "a alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"a\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "b packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"b\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "b alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"b\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "g packed alu.v(176) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(176): data type declaration for \"g\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 176 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "g alu.v(177) " "Info (10151): Verilog HDL Declaration information at alu.v(177): \"g\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 177 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "out packed alu.v(178) " "Warning (10227): Verilog HDL Port Declaration warning at alu.v(178): data type declaration for \"out\" declares packed dimensions but the port declaration declaration does not" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 178 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "out alu.v(179) " "Info (10151): Verilog HDL Declaration information at alu.v(179): \"out\" is declared here" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 179 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Info: Elaborating entity \"alu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 8 alu.v(84) " "Warning (10230): Verilog HDL assignment warning at alu.v(84): truncated value with size 9 to match size of target (8)" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 8 alu.v(49) " "Warning (10230): Verilog HDL assignment warning at alu.v(49): truncated value with size 9 to match size of target (8)" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "a\[8\] " "Warning (15610): No output dependent on input pin \"a\[8\]\"" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "b\[8\] " "Warning (15610): No output dependent on input pin \"b\[8\]\"" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "g\[8\] " "Warning (15610): No output dependent on input pin \"g\[8\]\"" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1373 " "Info: Implemented 1373 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "38 " "Info: Implemented 38 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1327 " "Info: Implemented 1327 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "149 " "Info: Allocated 149 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 15 10:29:21 2008 " "Info: Processing ended: Sat Mar 15 10:29:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:50 " "Info: Elapsed time: 00:00:50" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}