prev_cmp_alu.tan.qmsg

用VERILOG实现ALU

{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[0\] out\[0\]~reg0 6.423 ns register " "Info: tco from clock \"clk\" to destination pin \"out\[0\]\" through register \"out\[0\]~reg0\" is 6.423 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.464 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.649 ns) + CELL(0.618 ns) 2.464 ns out\[0\]~reg0 3 REG LCFF_X15_Y10_N13 1 " "Info: 3: + IC(0.649 ns) + CELL(0.618 ns) = 2.464 ns; Loc. = LCFF_X15_Y10_N13; Fanout = 1; REG Node = 'out\[0\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.267 ns" { clk~clkctrl out[0]~reg0 } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.74 % ) " "Info: Total cell delay = 1.472 ns ( 59.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.992 ns ( 40.26 % ) " "Info: Total interconnect delay = 0.992 ns ( 40.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.464 ns" { clk clk~clkctrl out[0]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.464 ns" { clk {} clk~combout {} clk~clkctrl {} out[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.649ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.865 ns + Longest register pin " "Info: + Longest register to pin delay is 3.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out\[0\]~reg0 1 REG LCFF_X15_Y10_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y10_N13; Fanout = 1; REG Node = 'out\[0\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { out[0]~reg0 } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.721 ns) + CELL(2.144 ns) 3.865 ns out\[0\] 2 PIN PIN_N1 0 " "Info: 2: + IC(1.721 ns) + CELL(2.144 ns) = 3.865 ns; Loc. = PIN_N1; Fanout = 0; PIN Node = 'out\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.865 ns" { out[0]~reg0 out[0] } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 55.47 % ) " "Info: Total cell delay = 2.144 ns ( 55.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.721 ns ( 44.53 % ) " "Info: Total interconnect delay = 1.721 ns ( 44.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.865 ns" { out[0]~reg0 out[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.865 ns" { out[0]~reg0 {} out[0] {} } { 0.000ns 1.721ns } { 0.000ns 2.144ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.464 ns" { clk clk~clkctrl out[0]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.464 ns" { clk {} clk~combout {} clk~clkctrl {} out[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.649ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.865 ns" { out[0]~reg0 out[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.865 ns" { out[0]~reg0 {} out[0] {} } { 0.000ns 1.721ns } { 0.000ns 2.144ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "out\[6\]~reg0 b\[6\] clk -2.550 ns register " "Info: th for register \"out\[6\]~reg0\" (data pin = \"b\[6\]\", clock pin = \"clk\") is -2.550 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.462 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.647 ns) + CELL(0.618 ns) 2.462 ns out\[6\]~reg0 3 REG LCFF_X14_Y10_N13 1 " "Info: 3: + IC(0.647 ns) + CELL(0.618 ns) = 2.462 ns; Loc. = LCFF_X14_Y10_N13; Fanout = 1; REG Node = 'out\[6\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.265 ns" { clk~clkctrl out[6]~reg0 } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.79 % ) " "Info: Total cell delay = 1.472 ns ( 59.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 40.21 % ) " "Info: Total interconnect delay = 0.990 ns ( 40.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.462 ns" { clk clk~clkctrl out[6]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.462 ns" { clk {} clk~combout {} clk~clkctrl {} out[6]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.647ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.161 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.837 ns) 0.837 ns b\[6\] 1 PIN PIN_W13 65 " "Info: 1: + IC(0.000 ns) + CELL(0.837 ns) = 0.837 ns; Loc. = PIN_W13; Fanout = 65; PIN Node = 'b\[6\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[6] } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.116 ns) + CELL(0.053 ns) 5.006 ns Mux1~54 2 COMB LCCOMB_X14_Y10_N12 1 " "Info: 2: + IC(4.116 ns) + CELL(0.053 ns) = 5.006 ns; Loc. = LCCOMB_X14_Y10_N12; Fanout = 1; COMB Node = 'Mux1~54'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.169 ns" { b[6] Mux1~54 } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.161 ns out\[6\]~reg0 3 REG LCFF_X14_Y10_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.161 ns; Loc. = LCFF_X14_Y10_N13; Fanout = 1; REG Node = 'out\[6\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Mux1~54 out[6]~reg0 } "NODE_NAME" } } { "alu.v" "" { Text "C:/Documents and Settings/Administrator/桌面/仿真/3/alu.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.045 ns ( 20.25 % ) " "Info: Total cell delay = 1.045 ns ( 20.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.116 ns ( 79.75 % ) " "Info: Total interconnect delay = 4.116 ns ( 79.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.161 ns" { b[6] Mux1~54 out[6]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.161 ns" { b[6] {} b[6]~combout {} Mux1~54 {} out[6]~reg0 {} } { 0.000ns 0.000ns 4.116ns 0.000ns } { 0.000ns 0.837ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.462 ns" { clk clk~clkctrl out[6]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "2.462 ns" { clk {} clk~combout {} clk~clkctrl {} out[6]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.647ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.161 ns" { b[6] Mux1~54 out[6]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.161 ns" { b[6] {} b[6]~combout {} Mux1~54 {} out[6]~reg0 {} } { 0.000ns 0.000ns 4.116ns 0.000ns } { 0.000ns 0.837ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 15 10:29:42 2008 " "Info: Processing ended: Sat Mar 15 10:29:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}