pc.v

用VERILOG实现ALU

module pc(clk,reset,ia)
input clk,reset;
output ia;
reg [4:0] ia;
 
always @(reset)  //difference between DFF and D-latch
  begin
  if(reset==0)
     ia<=4'b00000;
   wait(reset!=0); //其中wait 为电平控制，与posedge 和negedge不一样的是，他们是触发控制

  end
  

always @(posedge clk)
  if(ia==4'b11111)
     ia<=4'b00000;
  else 
    ia<=ia+1;

endmodule