alu.map.summary

用VERILOG实现ALU

Analysis & Synthesis Status : Successful - Sat Mar 15 10:29:21 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : alu
Top-level Entity Name : alu
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 1,327
    Dedicated logic registers : 8
Total registers : 8
Total pins : 46
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0