alu.v.bak

用VERILOG实现ALU

module alu(out,a,b,g,n,clk,ALUFN);

parameter m=16;
input  a,b,g,n,clk,ALUFN;
wire [m:0] a,b,g;
wire [m-1:0] n;
wire [1:0] ALUFN;
output out;
reg [m-1:0] out;
reg t[m:0][m:0];
reg z[m:0][m:0];
integer j,i,k,l;
//wire [m:0] n;
//assign n=2^m-1;

initial
begin

for(i=0;i<=m;i=i+1)
   for(k=0;k<=m;k=k+1)
       begin
      t[i][k]=0;
      z[i][k]=0;
      end
   
end

always @(posedge clk)
begin

case(ALUFN)
    2'b00: add(a,b,g,out);  //ADD
    2'b01: mul(a,b,g,out);  //MUL
    2'b10: expon(a,g,n,out);  //EXP
    2'b11: div(a,b,g,out);    //DIV
endcase

end


task div;
input  a,b,g;
wire [m:0] a,b,g;
output out;
reg [m-1:0] out;

begin
  
   out=b;
  

   for(j=m-2;j>=1;j=j-1)
 
     begin
 
           mul({1'b0,out},{1'b0,out},g,out);  //MUL 
           mul({1'b0,out},b,g,out);  //MUL 
    
      end
   
    mul({1'b0,out},{1'b0,out},g,out);  //MUL 
    mul({1'b0,out},a,g,out);  //MUL 

end


endtask





task expon;

input  a,g,n;
wire [m:0] a,g;
wire [m-1:0] n;
output out;
reg [m-1:0] out;

 
begin
  if (n[m-1]==1) 
     out=a;
  else 
     out='b1;


for(j=m-2;j>=0;j=j-1)
 
  begin

    if (n[j]==1) 
       begin 
           mul({1'b0,out},{1'b0,out},g,out);  //MUL 
           mul({1'b0,out},a,g,out);  //MUL 
        end
    else 
        begin 
           mul({1'b0,out},{1'b0,out},g,out);  //MUL 
           mul({1'b0,out},'b1,g,out);  //MUL 
        end
  end
 

end


endtask






task mul;

//parameter m=8;
input  a,b,g;
wire [m:0] a,b,g;
output out;
reg [m-1:0] out;
//reg t[m:0][m:0];
//reg z[m:0][m:0];
//integer j,i,k,l;


begin

for(i=1;i<=m;i=i+1)
   for(k=m-1;k>=0;k=k-1)
       begin
       
        if(k==0)        
         z[i][k]=0;         
       else 
          z[i][k]=t[i-1][k-1];
     
    basic(z[i][k],g[k],a[k],t[i-1][m-1],b[m-i],t[i][k]);
         
        end 


 for(l=1;l<=m;l=l+1)
    out[l-1]=t[m][l-1];


end  


endtask





task basic;

input   t2,g1,a1,t1,b1;
output  t3;
reg  v1,v2;
begin

     v1=b1&a1;   
     v2=t1&g1;
   t3=v1^v2^t2;
   
end

endtask


task add;

//parameter m=8;
input  a,b,g;
wire [m:0] a,b,g;
output out;
reg [m-1:0] out;

out=a[m-1:0]^b[m-1:0];


endtask



endmodule