regfile.v

用VERILOG实现ALU

module regfile(clk,reset,regwr,in_address,radata,rbdata,wdata);
parameter n=256,m=8,l=4;
input clk,reset,regwr,in_address,radata,rbdata;
output wdata;
wire [m-1:0] radata,rbdata;
wire [3*l-1:0] in_address;
reg [m-1:0] wdata;
reg [m-1:0]ram [n-1:0];
reg [l-1:0] ra,rb,rw;


   begin
          rw=in_address[l-1:0];
          rb=in_address[2*l-1:l];
          ra=in_address[3*l-1:2*l];
          radata=regfile[ra];
          rbdata=regfile[rb];
   end

always @(posedge clk)
   begin
       
       if( regwr==1)  
          
    regfile[rw]=wdata;
          
   end

end

endmodule