ar5211_attach.c

Atheros wifi driver source code

			"this driver\n", __func__,
			AH_PRIVATE(ah)->ah_analog5GhzRev);
		ecode = HAL_ENOTSUPP;
		goto bad;
	}

	if (!ar5211EepromRead(ah, AR_EEPROM_VERSION, &eeval)) {
		HALDEBUG(ah, "%s: unable to read EEPROM version\n", __func__);
		ecode = HAL_EEREAD;
		goto bad;
	}
	if (eeval < AR_EEPROM_VER3) {
		HALDEBUG(ah, "%s: unsupported EEPROM version "
			"%u (0x%x) found\n", __func__, eeval, eeval);
		ecode = HAL_EEVERSION;
		goto bad;
	}
	ahp->ah_eeversion = eeval;

	val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >>
               AR_PCICFG_EEPROM_SIZE_S;
	if (val != AR_PCICFG_EEPROM_SIZE_16K) {
		HALDEBUG(ah, "%s: unsupported EEPROM size "
			"%u (0x%x) found\n", __func__, val, val);
		ecode = HAL_EESIZE;
		goto bad;
	}

	if (!ar5211EepromRead(ah, AR_EEPROM_PROTECT, &eeval)) {
		HALDEBUG(ah, "%s: cannot read EEPROM protection "
			"bits; read locked?\n", __func__);
		ecode = HAL_EEREAD;
		goto bad;
	}
	HALDEBUG(ah, "EEPROM protect 0x%x\n", eeval);
	ahp->ah_eeprotect = eeval;
	/* XXX check proper access before continuing */

	/*
	 * Read the Atheros EEPROM entries and calculate the checksum.
	 */
	sum = 0;
	for (i = 0; i < AR_EEPROM_ATHEROS_MAX; i++) {
		if (!ar5211EepromRead(ah, AR_EEPROM_ATHEROS(i), &eeval)) {
			ecode = HAL_EEREAD;
			goto bad;
		}
		sum ^= eeval;
	}
	if (sum != 0xffff) {
		HALDEBUG(ah, "%s: bad EEPROM checksum 0x%x\n", __func__, sum);
		ecode = HAL_EEBADSUM;
		goto bad;
	}

	ahp->ah_numChannels11a = NUM_11A_EEPROM_CHANNELS;
	ahp->ah_numChannels2_4 = NUM_2_4_EEPROM_CHANNELS;

	for (i = 0; i < NUM_11A_EEPROM_CHANNELS; i ++)
		ahp->ah_dataPerChannel11a[i].numPcdacValues = NUM_PCDAC_VALUES;

	/* the channel list for 2.4 is fixed, fill this in here */
	for (i = 0; i < NUM_2_4_EEPROM_CHANNELS; i++) {
		ahp->ah_channels11b[i] = channels2_4[i];
		ahp->ah_channels11g[i] = channels2_4[i];
		ahp->ah_dataPerChannel11b[i].numPcdacValues = NUM_PCDAC_VALUES;
		ahp->ah_dataPerChannel11g[i].numPcdacValues = NUM_PCDAC_VALUES;
	}

	if (!ath_hal_readEepromIntoDataset(ah, &ahp->ah_eeprom)) {
		ecode = HAL_EEREAD;	/* XXX */
		goto bad;
        }

        /* If Bmode and AR5211, verify 2.4 analog exists */
	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU &&
	    ahp->ah_Bmode) {
		/* Set correct Baseband to analog shift setting to access analog chips. */
		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);
		OS_DELAY(2000);
		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah);

		/* Set baseband for 5GHz chip */
		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
		OS_DELAY(2000);
		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) {
			HALDEBUG(ah, "%s: 2G Radio Chip Rev 0x%x is "
				"not supported by this driver\n",
				__func__, AH_PRIVATE(ah)->ah_analog2GhzRev);
			ecode = HAL_ENOTSUPP;
			goto bad;
		}
	} else {
		ahp->ah_Bmode = 0;
        }

        if (!ar5211EepromRead(ah, AR_EEPROM_REG_DOMAIN, &eeval)) {
		HALDEBUG(ah, "%s: cannot read regulator domain from EEPROM\n",
			__func__);
		ecode = HAL_EEREAD;
		goto bad;
        }
	ahp->ah_regdomain = eeval;
	AH_PRIVATE(ah)->ah_currentRD = ahp->ah_regdomain;
	AH_PRIVATE(ah)->ah_radarAttach = ar5211RadarAttach;
	AH_PRIVATE(ah)->ah_radarDetach = ar5211RadarDetach;

	/*
	 * Got everything we need now to setup the capabilities.
	 */
	(void) ar5211FillCapabilityInfo(ah);

	/* Initialize gain ladder thermal calibration structure */
	ar5211InitializeGainValues(ah);

	sum = 0;
	for (i = 0; i < 3; i++) {
		if (!ar5211EepromRead(ah, AR_EEPROM_MAC(2-i), &eeval)) {
			HALDEBUG(ah, "%s: cannot read EEPROM "
				"location %u\n", __func__, i);
			ecode = HAL_EEREAD;
			goto bad;
		}
		sum += eeval;
		ahp->ah_macaddr[2*i] = eeval >> 8;
		ahp->ah_macaddr[2*i + 1] = eeval & 0xff;
	}
	if (sum == 0 || sum == 0xffff*3) {
		HALDEBUG(ah, "%s: mac address read failed: %s\n",
		    __func__, ath_hal_ether_sprintf(ahp->ah_macaddr));
		ecode = HAL_EEBADMAC;
		goto bad;
	}

	HALDEBUG(ah, "%s: return ah %p\n", __func__, ah);

	return ah;
bad:
	if (ahp)
		ar5211Detach((struct ath_hal *) ahp);
	if (status)
		*status = ecode;
	return AH_NULL;
#undef N
}

void
ar5211Detach(struct ath_hal *ah)
{
	HALDEBUG(ah, "%s: ah %p\n", __func__, ah);

	HALASSERT(ah != AH_NULL);
	HALASSERT(ah->ah_magic == AR5211_MAGIC);

	ath_hal_free(ah);
}

static HAL_BOOL
ar5211ChipTest(struct ath_hal *ah)
{
	u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
	u_int32_t regHold[2];
	u_int32_t patternData[4] =
	    { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
	int i, j;

	/* Test PHY & MAC registers */
	for (i = 0; i < 2; i++) {
		u_int32_t addr = regAddr[i];
		u_int32_t wrData, rdData;

		regHold[i] = OS_REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			OS_REG_WRITE(ah, addr, wrData);
			rdData = OS_REG_READ(ah, addr);
			if (rdData != wrData) {
				HALDEBUG(ah,
"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
				__func__, addr, wrData, rdData);
				return AH_FALSE;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			OS_REG_WRITE(ah, addr, wrData);
			rdData = OS_REG_READ(ah, addr);
			if (wrData != rdData) {
				HALDEBUG(ah,
"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
					__func__, addr, wrData, rdData);
				return AH_FALSE;
			}
		}
		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
	}
	OS_DELAY(100);
	return AH_TRUE;
}

/*
 * Store the channel edges for the requested operational mode
 */
static HAL_BOOL
ar5211GetChannelEdges(struct ath_hal *ah,
	u_int16_t flags, u_int16_t *low, u_int16_t *high)
{
	if (flags & CHANNEL_5GHZ) {
		*low = 4920;
		*high = 6100;
		return AH_TRUE;
	}
	if (flags & CHANNEL_2GHZ && AH5211(ah)->ah_Bmode) {
		*low = 2312;
		*high = 2732;
		return AH_TRUE;
	}
	return AH_FALSE;
}

static HAL_BOOL
ar5211GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, u_int32_t nchans)
{
	/* XXX fill in */
	return AH_TRUE;
}

/*
 * Fill all software cached or static hardware state information.
 */
static HAL_BOOL
ar5211FillCapabilityInfo(struct ath_hal *ah)
{
	struct ath_hal_5211 *ahp = AH5211(ah);
	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;

        /* TODO: Remove this hack to fix bad reg domains */
        if (AH_PRIVATE(ah)->ah_currentRD == 1) {
		HAL_STATUS ecode;

		HALDEBUG(ah, "Warning, fixing regulatory domain of 1\n");
		/* XXX check return value */
		ar5211SetRegulatoryDomain(ah, 0x10, &ecode);
        }

	/* Construct wireless mode from EEPROM */
	pCap->halWirelessModes = 0;
	if (ahp->ah_Amode) {
		pCap->halWirelessModes |= HAL_MODE_11A;
		if (!ahp->ah_turbo5Disable)
			pCap->halWirelessModes |= HAL_MODE_TURBO;
	}
	if (ahp->ah_Bmode)
		pCap->halWirelessModes |= HAL_MODE_11B;

	pCap->halLow2GhzChan = 2312;
	pCap->halHigh2GhzChan = 2732;
	pCap->halLow5GhzChan = 4920;
	pCap->halHigh5GhzChan = 6100;

	pCap->halChanSpreadSupport = AH_TRUE;
	pCap->halSleepAfterBeaconBroken = AH_TRUE;
	pCap->halPSPollBroken = AH_TRUE;
	pCap->halVEOLSupport = AH_TRUE;

	pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
	pCap->halKeyCacheSize = 128;

	pCap->halChanHalfRate = AH_FALSE;
	pCap->halChanQuarterRate = AH_FALSE;

	return AH_TRUE;
}
#endif /* AH_SUPPORT_AR5211 */