ar5416_eeprom.c

Atheros wifi driver source code

0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};

static void ar5416FillEmuEeprom(struct ath_hal *ahp);
static HAL_BOOL ar5416FillEeprom(struct ath_hal *ah);
static HAL_STATUS ar5416CheckEeprom(struct ath_hal *ah);
static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
                           ar5416_eeprom_t *pEepData, HAL_HT *ht,
                           HAL_CHANNEL_INTERNAL *chan, int16_t *ratesArray,
                           u_int16_t cfgCtl, u_int16_t AntennaReduction,
                           u_int16_t twiceMaxRegulatoryPower, 
                           u_int16_t powerLimit);
static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
			HAL_HT *ht, ar5416_eeprom_t *pEepData,
			HAL_CHANNEL_INTERNAL *chan,
			int16_t *pTxPowerIndexOffset);
static u_int16_t ar5416GetMaxEdgePower(u_int16_t freq,
			CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
static void ar5416GetTargetPowers(struct ath_hal *ah, HAL_HT *ht,
			HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_HT *powInfo,
			u_int16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
			u_int16_t numRates, HAL_BOOL isHt40Target);
static void ar5416GetTargetPowersLeg(struct ath_hal *ah, HAL_HT *ht,
			HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_LEG *powInfo,
			u_int16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
			u_int16_t numRates, HAL_BOOL isExtTarget);

static u_int16_t fbin2freq(u_int8_t fbin, HAL_BOOL is2GHz);
static int16_t interpolate(u_int16_t target, u_int16_t srcLeft,
			u_int16_t srcRight, int16_t targetLeft,
			int16_t targetRight);
static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, HAL_HT *ht,
                        HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet,
                        u_int8_t * bChans, u_int16_t availPiers,
                        u_int16_t tPdGainOverlap, int16_t *pMinCalPower,
                        u_int16_t * pPdGainBoundaries, u_int8_t * pPDADCValues,
                        u_int16_t numXpdGains);
static HAL_BOOL getLowerUpperIndex(u_int8_t target, u_int8_t *pList,
			u_int16_t listSize,  u_int16_t *indexL,
 			u_int16_t *indexR);
static HAL_BOOL ar5416FillVpdTable(u_int8_t pwrMin, u_int8_t pwrMax,
			u_int8_t *pPwrList, u_int8_t *pVpdList,
			u_int16_t numIntercepts, u_int8_t *pRetVpdList);
			  
static u_int16_t ar5416EepromGetSpurChan(struct ath_hal *ah, u_int16_t spurChan,HAL_BOOL is2GHz);
static HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, u_int32_t nchans);
static HAL_BOOL ar5416GetEepromCapabilityInfo(struct ath_hal *ah, u_int16_t *capField);
static void ar5416ReadEepromCTLInfo(struct ath_hal *ah);

/* Functions exported via attach */
//HAL_STATUS ar5416EepromAttach(struct ath_hal *ah);
static HAL_STATUS ar5416EepromDetach(struct ath_hal *ah);
static u_int32_t ar5416EepromGet(struct ath_hal *ahp, EEPROM_PARAM param);
static HAL_BOOL ar5416EepromSetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan);
static HAL_BOOL ar5416SetTransmitPower(struct ath_hal *ah, 
	HAL_CHANNEL_INTERNAL *chan, u_int16_t *rfXpdGain);
static HAL_BOOL ar5416GetEepromNoiseFloorThresh(struct ath_hal *ah, 
			const HAL_CHANNEL_INTERNAL *chan, int16_t *nft);
#ifdef EEPROM_DUMP	
static void ar5416PrintPowerPerRate(struct ath_hal *ah, int16_t pRatesPower[]);
static void ar5416EepromDump(struct ath_hal *ah, ar5416_eeprom_t *ar5416Eep);
#endif
/*****************************
 * Eeprom APIs for CB/XB/MB only
 ****************************/

/*
 * Read 16 bits of data from offset into *data
 */
HAL_BOOL
ar5416EepromRead(struct ath_hal *ah, u_int off, u_int16_t *data)
{

	if (IS_5416_EMU_EEP(ah)) {
        	off = off & (OWLEMU_EEPROM_SZ - 1);
        	*data = owlemu_eeprom[off];
		return AH_TRUE;
	} else {

        	(void)OS_REG_READ(ah,  AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S) );
       		if (!ath_hal_wait(ah, AR_EEPROM_STATUS_DATA, AR_EEPROM_STATUS_DATA_BUSY
				| AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
            	return AH_FALSE;
        	}

       	 	*data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA), AR_EEPROM_STATUS_DATA_VAL);
        	return AH_TRUE;
	}

}

#ifdef AH_SUPPORT_WRITE_EEPROM
/*
 * Write 16 bits of data from data to the specified EEPROM offset.
 */
HAL_BOOL
ar5416EepromWrite(struct ath_hal *ah, u_int off, u_int16_t data)
{
	if (!IS_5416_EMU_EEP(ah))
		OS_REG_WR(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S), data);
        return AH_TRUE;
}
#endif /* AH_SUPPORT_WRITE_EEPROM */

/*************************
 * Flash APIs for AP only
 *************************/
#if 0
HAL_STATUS
ar5416FlashMap(struct ath_hal *ah)
{
    struct ath_hal *ahp = AH5416(ah);

    ahp->ah_cal_mem = OS_REMAP(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
    if (!ahp->ah_cal_mem) {
        HALDEBUG(ah, "%s: cannot remap eeprom region \n", __func__);
        return HAL_EIO;
    }

    return HAL_OK;
}

HAL_BOOL
ar5416FlashRead(struct ath_hal *ah, u_int off, u_int16_t *data)
{
    struct ath_hal *ahp = AH5416(ah);

    *data = ((u_int16_t *)ahp->ah_cal_mem)[off];
    return AH_TRUE;
}

HAL_BOOL
ar5416FlashWrite(struct ath_hal *ah, u_int off, u_int16_t data)
{
    struct ath_hal *ahp = AH5416(ah);

    ((u_int16_t *)ahp->ah_cal_mem)[off] = data;
    return AH_TRUE;
}
#endif
/***************************
 * Common APIs for AP/CB/XB
 ***************************/

HAL_STATUS
ar5416EepromAttach(struct ath_hal *ah)
{
    struct ath_hal_5416 *ahp = AH5416(ah);
    HAL_STATUS status;

    AH_PRIVATE(ah)->ah_eepromRead = ar5416EepromRead;
    AH_PRIVATE(ah)->ah_eepromDetach = ar5416EepromDetach;
    AH_PRIVATE(ah)->ah_eepromSetBoardValues = ar5416EepromSetBoardValues;
    AH_PRIVATE(ah)->ah_eepromGetSpurChan =  ar5416EepromGetSpurChan;
    AH_PRIVATE(ah)->ah_setTransmitPower = ar5416SetTransmitPower;
    AH_PRIVATE(ah)->ah_getChipPowerLimits = ar5416GetChipPowerLimits;
    AH_PRIVATE(ah)->ah_getEepromCapabilityInfo = ar5416GetEepromCapabilityInfo;
    AH_PRIVATE(ah)->ah_getEepromNoiseFloorThresh = ar5416GetEepromNoiseFloorThresh;

    //owl_eeprom_map(ah);
    /* Allocate memory for copy of eeprom */
    ahp->ah_5416eeprom = ath_hal_malloc(sizeof(ar5416_eeprom_t));
    if (ahp->ah_5416eeprom == AH_NULL) {
    	HALDEBUG(ah, "%s: Failed memory allocation for eeprom\n", __func__);
    	return HAL_ENOMEM;
    }

    ath_hal_memzero(ahp->ah_5416eeprom,sizeof(ar5416_eeprom_t));

    if (IS_5416_EMU_EEP(ah)) { 
    	ar5416FillEmuEeprom((struct ath_hal *)ahp);
	return HAL_OK;
    }

    if (!ar5416FillEeprom(ah)){
    	HALDEBUG(ah,"%s Error reading AR5416/AR5418 Eeprom.\n",__func__);
        return HAL_EIO;
    }

    if ((status = ar5416CheckEeprom(ah)) != HAL_OK) {
    	HALDEBUG(ah,"%s AR5416/AR5418 Eeprom failed check.\n",__func__);
    	return status;
    }
     /* Get CTLs */
    ar5416ReadEepromCTLInfo(ah);
    
    HALDEBUG(ah,"%s ahp->ah_5416eeprom=0x%p\n",__func__, ahp->ah_5416eeprom);

    return HAL_OK;
}
static HAL_STATUS
ar5416EepromDetach(struct ath_hal *ah) {
	struct ath_hal_5416 *ahp = AH5416(ah);
	
	if (ahp->ah_5416eeprom)
		ath_hal_free(ahp->ah_5416eeprom);
		
	return HAL_OK;
}
static u_int32_t
ar5416EepromGet(struct ath_hal *ahp, EEPROM_PARAM param)
{
    ar5416_eeprom_t *eep = (ar5416_eeprom_t *)(AH5416(ahp)->ah_5416eeprom);
    MODAL_EEP_HEADER *pModal = eep->modalHeader;
    BASE_EEP_HEADER  *pBase  = &eep->baseEepHeader;

    switch (param) {
        case EEP_NFTHRESH_5:
    	 /* 5GHz Threshold is a signed value.
	  * Use cast to ensure proper sign extension
	  */	
            return (int8_t)pModal[0].noiseFloorThreshCh[0];
        case EEP_NFTHRESH_2:
	 /* 2GHz Threshold is a signed value. 
	  * Use cast to ensure proper sign extension
	  */
            return (int8_t)pModal[1].noiseFloorThreshCh[0];
        case AR_EEPROM_MAC(0):
            return pBase->macAddr[0] << 8 | pBase->macAddr[1];
        case AR_EEPROM_MAC(1):
            return pBase->macAddr[2] << 8 | pBase->macAddr[3];
        case AR_EEPROM_MAC(2):
            return pBase->macAddr[4] << 8 | pBase->macAddr[5];
        case EEP_REG_0:
            return pBase->regDmn[0];
        case EEP_REG_1:
            return pBase->regDmn[1];
        case EEP_OP_CAP:
            return pBase->deviceCap;
        case EEP_OP_MODE:
            return pBase->opCapFlags;
        case EEP_RF_SILENT:
            return pBase->rfSilent;
        default:
            HALASSERT(0);
            return 0;
    }
}

/*
 * Read EEPROM header info and program the device for correct operation
 * given the channel value.
 */
static HAL_BOOL
ar5416EepromSetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{
    MODAL_EEP_HEADER *pModal;
    int i, regChainOffset;
    struct ath_hal_5212 *ahp = AH5416(ah);
    ar5416_eeprom_t *eep = (ar5416_eeprom_t *)ahp->ah_5416eeprom;

    HALASSERT(owl_get_eep_ver(ahp) == AR5416_EEP_VER);
    pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);

    if (IS_5416_EMU_EEP(ah))
        return AH_TRUE;

    OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
    for (i = 0; i < AR5416_MAX_CHAINS; i++) {
       // if((AH_PRIVATE(ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) && 
       	   if (!(IS_5416V1(ah)) &&
           (eep->baseEepHeader.txMask == 0x5) && (i != 0)) {
            /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 
             * only chains 0 and 2 populated 
             */
            regChainOffset = (i == 1) ? 0x2000 : 0x1000;
        } else {
            regChainOffset = i * 0x1000;
        }

        OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
        OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 
        (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
        ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
        SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
        SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));

        if ((i == 0) || !IS_5416V1(ah)) {
            //(AH_PRIVATE(ah)->ah_macRev >= AR_SREV_REVISION_OWL_20)) {
            OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 
            (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
            SM(pModal->txRxAttenCh[i], AR_PHY_RXGAIN_TXRX_ATTEN));
            OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
                SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
        }
    }