ar5212reg.h

Atheros wifi driver source code

#define	AR_IMR_S0_QCU_TXOK	0x000003FF /* TXOK (QCU 0-9) */
#define	AR_IMR_S0_QCU_TXOK_S	0
#define	AR_IMR_S0_QCU_TXDESC	0x03FF0000 /* TXDESC (QCU 0-9) */
#define	AR_IMR_S0_QCU_TXDESC_S	16

#define	AR_IMR_S1_QCU_TXERR	0x000003FF /* TXERR (QCU 0-9) */
#define	AR_IMR_S1_QCU_TXERR_S	0
#define	AR_IMR_S1_QCU_TXEOL	0x03FF0000 /* TXEOL (QCU 0-9) */
#define	AR_IMR_S1_QCU_TXEOL_S	16

#define	AR_IMR_S2_QCU_TXURN	0x000003FF /* Mask for TXURN (QCU 0-9) */
#define	AR_IMR_S2_QCU_TXURN_S	0
#define	AR_IMR_S2_MCABT		0x00010000 /* Master cycle abort interrupt */
#define	AR_IMR_S2_SSERR		0x00020000 /* SERR interrupt */
#define	AR_IMR_S2_DPERR		0x00040000 /* PCI bus parity error */
#define	AR_IMR_S2_TIM		0x01000000 /* TIM */
#define	AR_IMR_S2_CABEND	0x02000000 /* CABEND */
#define	AR_IMR_S2_DTIMSYNC	0x04000000 /* DTIMSYNC */
#define	AR_IMR_S2_BCNTO		0x08000000 /* BCNTO */
#define	AR_IMR_S2_CABTO		0x10000000 /* CABTO */
#define	AR_IMR_S2_DTIM		0x20000000 /* DTIM */
#define	AR_IMR_S2_RESV0		0xE0F8FC00 /* Reserved */

#define	AR_IMR_S3_QCU_QCBROVF	0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define	AR_IMR_S3_QCU_QCBRURN	0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define	AR_IMR_S3_QCU_QCBRURN_S	16         /* Shift for QCBRURN (QCU 0-9) */

#define	AR_IMR_S4_QCU_QTRIG	0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define	AR_IMR_S4_RESV0		0xFFFFFC00 /* Reserved */

/* QCU registers */
#define	AR_NUM_QCU	10     /* Only use QCU 0-9 for forward QCU compatibility */
#define	AR_QCU_0	0x0001
#define	AR_QCU_1	0x0002
#define	AR_QCU_2	0x0004
#define	AR_QCU_3	0x0008
#define	AR_QCU_4	0x0010
#define	AR_QCU_5	0x0020
#define	AR_QCU_6	0x0040
#define	AR_QCU_7	0x0080
#define	AR_QCU_8	0x0100
#define	AR_QCU_9	0x0200

#define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF /* Mask for CBR interval (us) */
#define AR_Q_CBRCFG_CBR_INTERVAL_S      0   /* Shift for CBR interval */
#define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000 /* Mask for CBR overflow threshold */
#define AR_Q_CBRCFG_CBR_OVF_THRESH_S    24  /* Shift for CBR overflow thresh */

#define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF /* CBR interval (us) */
#define AR_Q_RDYTIMECFG_INT_S   0  // Shift for ReadyTime Interval (us) */
#define	AR_Q_RDYTIMECFG_ENA	0x01000000 /* CBR enable */
/* bits 25-31 are reserved */

#define	AR_Q_MISC_FSP		0x0000000F /* Frame Scheduling Policy mask */
#define	AR_Q_MISC_FSP_ASAP		0	/* ASAP */
#define	AR_Q_MISC_FSP_CBR		1	/* CBR */
#define	AR_Q_MISC_FSP_DBA_GATED		2	/* DMA Beacon Alert gated */
#define	AR_Q_MISC_FSP_TIM_GATED		3	/* TIM gated */
#define	AR_Q_MISC_FSP_BEACON_SENT_GATED	4	/* Beacon-sent-gated */
#define	AR_Q_MISC_ONE_SHOT_EN	0x00000010 /* OneShot enable */
#define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020 /* Disable CBR expired counter incr
					      (empty q) */
#define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040 /* Disable CBR expired counter incr
					      (empty beacon q) */
#define	AR_Q_MISC_BEACON_USE	0x00000080 /* Beacon use indication */
#define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100 /* CBR expired counter limit enable */
#define	AR_Q_MISC_RDYTIME_EXP_POLICY	0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
#define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400 /* Reset CBR expired counter */
#define	AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800 /* DCU frame early termination request control */
#define	AR_Q_MISC_QCU_COMP_EN	0x00001000 /* QCU frame compression enable */
#define	AR_Q_MISC_RESV0		0xFFFFF000 /* Reserved */

#define	AR_Q_STS_PEND_FR_CNT	0x00000003 /* Mask for Pending Frame Count */
#define	AR_Q_STS_RESV0		0x000000FC /* Reserved */
#define	AR_Q_STS_CBR_EXP_CNT	0x0000FF00 /* Mask for CBR expired counter */
#define	AR_Q_STS_RESV1		0xFFFF0000 /* Reserved */

/* DCU registers */
#define	AR_NUM_DCU	10     /* Only use 10 DCU's for forward QCU/DCU compatibility */
#define	AR_DCU_0	0x0001
#define	AR_DCU_1	0x0002
#define	AR_DCU_2	0x0004
#define	AR_DCU_3	0x0008
#define	AR_DCU_4	0x0010
#define	AR_DCU_5	0x0020
#define	AR_DCU_6	0x0040
#define	AR_DCU_7	0x0080
#define	AR_DCU_8	0x0100
#define	AR_DCU_9	0x0200

#define	AR_D_QCUMASK		0x000003FF /* Mask for QCU Mask (QCU 0-9) */
#define	AR_D_QCUMASK_RESV0	0xFFFFFC00 /* Reserved */

#define	AR_D_LCL_IFS_CWMIN	0x000003FF /* Mask for CW_MIN */
#define	AR_D_LCL_IFS_CWMIN_S	0
#define	AR_D_LCL_IFS_CWMAX	0x000FFC00 /* Mask for CW_MAX */
#define	AR_D_LCL_IFS_CWMAX_S	10
#define	AR_D_LCL_IFS_AIFS	0x0FF00000 /* Mask for AIFS */
#define	AR_D_LCL_IFS_AIFS_S	20
/*
 *  Note:  even though this field is 8 bits wide the
 *  maximum supported AIFS value is 0xfc.  Setting the AIFS value
 *  to 0xfd 0xfe, or 0xff will not work correctly and will cause
 *  the DCU to hang.
 */
#define	AR_D_LCL_IFS_RESV0	0xF0000000 /* Reserved */

#define	AR_D_RETRY_LIMIT_FR_SH	0x0000000F /* frame short retry limit */
#define	AR_D_RETRY_LIMIT_FR_SH_S	0
#define	AR_D_RETRY_LIMIT_FR_LG	0x000000F0 /* frame long retry limit */
#define	AR_D_RETRY_LIMIT_FR_LG_S	4
#define	AR_D_RETRY_LIMIT_STA_SH	0x00003F00 /* station short retry limit */
#define	AR_D_RETRY_LIMIT_STA_SH_S	8
#define	AR_D_RETRY_LIMIT_STA_LG	0x000FC000 /* station short retry limit */
#define	AR_D_RETRY_LIMIT_STA_LG_S	14
#define	AR_D_RETRY_LIMIT_RESV0		0xFFF00000 /* Reserved */

#define	AR_D_CHNTIME_DUR		0x000FFFFF /* ChannelTime duration (us) */
#define AR_D_CHNTIME_DUR_S              0 /* Shift for ChannelTime duration */
#define	AR_D_CHNTIME_EN			0x00100000 /* ChannelTime enable */
#define	AR_D_CHNTIME_RESV0		0xFFE00000 /* Reserved */

#define	AR_D_MISC_BKOFF_THRESH	0x0000003F /* Backoff threshold */
#define	AR_D_MISC_ETS_RTS		0x00000040 /* End of transmission series
						      station RTS/data failure
						      count reset policy */
#define	AR_D_MISC_ETS_CW		0x00000080 /* End of transmission series
						      CW reset policy */
#define AR_D_MISC_FRAG_WAIT_EN          0x00000100 /* Wait for next fragment */
#define AR_D_MISC_FRAG_BKOFF_EN         0x00000200 /* Backoff during a frag burst */
#define	AR_D_MISC_HCF_POLL_EN		0x00000800 /* HFC poll enable */
#define	AR_D_MISC_BKOFF_PERSISTENCE	0x00001000 /* Backoff persistence factor
						      setting */
#define	AR_D_MISC_FR_PREFETCH_EN	0x00002000 /* Frame prefetch enable */
#define	AR_D_MISC_VIR_COL_HANDLING	0x0000C000 /* Mask for Virtual collision
						      handling policy */

/* FOO redefined for venice CW increment policy */
#define	AR_D_MISC_VIR_COL_HANDLING_DEFAULT	0	/* Normal */
#define	AR_D_MISC_VIR_COL_HANDLING_IGNORE	1	/* Ignore */
#define	AR_D_MISC_BEACON_USE		0x00010000 /* Beacon use indication */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL	0x00060000 /* DCU arbiter lockout ctl */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_S	17         /* DCU arbiter lockout ctl */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE	0	/* No lockout */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR	1	/* Intra-frame */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL	2	/* Global */
#define	AR_D_MISC_ARB_LOCKOUT_IGNORE	0x00080000 /* DCU arbiter lockout ignore control */
#define	AR_D_MISC_SEQ_NUM_INCR_DIS	0x00100000 /* Sequence number increment disable */
#define	AR_D_MISC_POST_FR_BKOFF_DIS	0x00200000 /* Post-frame backoff disable */
#define	AR_D_MISC_VIRT_COLL_POLICY	0x00400000 /* Virtual coll. handling policy */
#define	AR_D_MISC_BLOWN_IFS_POLICY	0x00800000 /* Blown IFS handling policy */
#define	AR_D_MISC_RESV0			0xFE000000 /* Reserved */

#define	AR_D_SEQNUM_RESV0	0xFFFFF000 /* Reserved */

#define	AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL	0x00000007 /* LFSR slice select */
#define	AR_D_GBL_IFS_MISC_TURBO_MODE	0x00000008 /* Turbo mode indication */
#define	AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC	0x000003F0 /* SIFS duration (us) */
#define	AR_D_GBL_IFS_MISC_USEC_DURATION	0x000FFC00 /* microsecond duration */
#define	AR_D_GBL_IFS_MISC_USEC_DURATION_S 10
#define	AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY	0x00300000 /* DCU arbiter delay */
#define	AR_D_GBL_IFS_MISC_RESV0	0xFFC00000 /* Reserved */

/* DMA & PCI Registers in PCI space (usable during sleep) */
#define	AR_RC_MAC		0x00000001 /* MAC reset */
#define	AR_RC_BB		0x00000002 /* Baseband reset */
#define	AR_RC_RESV0		0x00000004 /* Reserved */
#define	AR_RC_RESV1		0x00000008 /* Reserved */
#define	AR_RC_PCI		0x00000010 /* PCI-core reset */

#define	AR_SCR_SLDUR		0x0000ffff /* sleep duration, units of 128us */
#define	AR_SCR_SLDUR_S		0
#define	AR_SCR_SLE		0x00030000 /* sleep enable */
#define	AR_SCR_SLE_S		16
#define	AR_SCR_SLE_WAKE		0 	/* force wake */
#define	AR_SCR_SLE_SLP		1	/* force sleep */
#define	AR_SCR_SLE_NORM		2	/* sleep logic normal operation */
#define	AR_SCR_SLDTP		0x00040000 /* sleep duration timing policy */
#define	AR_SCR_SLDWP		0x00080000 /* sleep duration write policy */
#define	AR_SCR_SLEPOL		0x00100000 /* sleep policy mode */

#define	AR_INTPEND_TRUE		0x00000001 /* interrupt pending */

#define	AR_SFR_SLEEP		0x00000001 /* force sleep */

#define	AR_PCICFG_SCLK_SEL	0x00000002 /* sleep clock select */
#define	AR_PCICFG_SCLK_SEL_S	1
#define	AR_PCICFG_CLKRUNEN	0x00000004 /* enable PCI CLKRUN function */
#define	AR_PCICFG_EEPROM_SIZE	0x00000018 /* Mask for EEPROM size */
#define	AR_PCICFG_EEPROM_SIZE_S		3	/* Mask for EEPROM size */
#define	AR_PCICFG_EEPROM_SIZE_4		0	/* EEPROM size 4 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_8K	1	/* EEPROM size 8 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_FAILED	3	/* Failure */
#define	AR_PCICFG_LEDCTL	0x00000060 /* LED control Status */
#define	AR_PCICFG_LEDCTL_NONE	0x00000000 /* STA is not associated or trying */
#define	AR_PCICFG_LEDCTL_PEND	0x00000020 /* STA is trying to associate */
#define	AR_PCICFG_LEDCTL_ASSOC	0x00000040 /* STA is associated */
#define	AR_PCICFG_PCI_BUS_SEL	0x00000380 /* PCI observation bus mux select */
#define	AR_PCICFG_DIS_CBE_FIX	0x00000400 /* Disable fix for bad PCI CBE# generation */
#define	AR_PCICFG_SL_INTEN	0x00000800 /* enable interrupt line assertion when asleep */
#define	AR_PCICFG_RESV0		0x00001000 /* Reserved */
#define	AR_PCICFG_SL_INPEN	0x00002000 /* Force asleep when an interrupt is pending */
#define	AR_PCICFG_RESV1		0x0000C000 /* Reserved */
#define	AR_PCICFG_SPWR_DN	0x00010000 /* mask for sleep/awake indication */
#define	AR_PCICFG_LEDMODE	0x000E0000 /* LED mode */
#define	AR_PCICFG_LEDMODE_PROP	0x00000000 /* Blink prop to filtered tx/rx */
#define	AR_PCICFG_LEDMODE_RPROP	0x00020000 /* Blink prop to unfiltered tx/rx */
#define	AR_PCICFG_LEDMODE_SPLIT	0x00040000 /* Blink power for tx/net for rx */
#define	AR_PCICFG_LEDMODE_RAND	0x00060000 /* Blink randomly */
#define	AR_PCICFG_LEDBLINK	0x00700000 /* LED blink threshold select */
#define	AR_PCICFG_LEDSLOW	0x00800000 /* LED slowest blink rate mode */
#define	AR_PCICFG_SCLK_RATE_IND 0x03000000 /* Sleep clock rate */
#define	AR_PCICFG_SCLK_RATE_IND_S 24
#define	AR_PCICFG_RESV2		0xFC000000 /* Reserved */

#define	AR_GPIOCR_CR_SHIFT	2          /* Each CR is 2 bits */
#define	AR_GPIOCR_CR_N(_g)	(0 << (AR_GPIOCR_CR_SHIFT * (_g)))
#define	AR_GPIOCR_CR_0(_g)	(1 << (AR_GPIOCR_CR_SHIFT * (_g)))
#define	AR_GPIOCR_CR_1(_g)	(2 << (AR_GPIOCR_CR_SHIFT * (_g)))
#define	AR_GPIOCR_CR_A(_g)	(3 << (AR_GPIOCR_CR_SHIFT * (_g)))
#define	AR_GPIOCR_INT_SHIFT	12         /* Interrupt select field shifter */
#define	AR_GPIOCR_INT(_g)	((_g) << AR_GPIOCR_INT_SHIFT)
#define	AR_GPIOCR_INT_MASK	0x00007000 /* Interrupt select field mask */
#define	AR_GPIOCR_INT_ENA	0x00008000 /* Enable GPIO Interrupt */
#define	AR_GPIOCR_INT_SELL	0x00000000 /* Generate int if pin is low */
#define	AR_GPIOCR_INT_SELH	0x00010000 /* Generate int if pin is high */
#define	AR_GPIOCR_INT_SEL	AR_GPIOCR_INT_SELH

#define	AR_SREV_ID		0x000000FF /* Mask to read SREV info */
#define	AR_SREV_ID_S		4          /* Mask to shift Major Rev Info */
#define	AR_SREV_REVISION	0x0000000F /* Mask for Chip revision level */
#define	AR_SREV_FPGA		1
#define	AR_SREV_D2PLUS		2
#define	AR_SREV_D2PLUS_MS	3	/* metal spin */
#define	AR_SREV_CRETE		4
#define	AR_SREV_CRETE_MS	5	/* FCS metal spin */
#define	AR_SREV_CRETE_MS23	7	/* 2.3 metal spin (6 skipped) */
#define	AR_SREV_CRETE_23	8	/* 2.3 full tape out */
#define AR_SREV_GRIFFIN_LITE    8
#define	AR_SREV_HAINAN  	9
#define AR_SREV_CONDOR		11
#define	AR_SREV_VERSION	0x000000F0 /* Mask for Chip version */
#define	AR_SREV_VERSION_CRETE	0
#define	AR_SREV_VERSION_MAUI_1	1
#define	AR_SREV_VERSION_MAUI_2	2
#define	AR_SREV_VERSION_SPIRIT	3