ar5212reg.h

Atheros wifi driver source code

#define DIAG_FORCE_RXCLR    (1<<20)     /* force rxclear (ignore CCA) */
#define DIAG_IGNORE_NAV     (1<<21)     /* ignore received nav */
#define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
#define	AR_TSF_U32	0x8050	/* MAC local clock upper 32 bits */
#define	AR_TST_ADDAC	0x8054	/* ADDAC test register */
#define	AR_DEF_ANTENNA	0x8058	/* default antenna register */
#define	AR_SEQ_MASK	0x8060	/* MAC AES mute mask */

#define	AR_LAST_TSTP	0x8080	/* MAC Time stamp of the last beacon received */
#define	AR_NAV		0x8084	/* MAC current NAV value */
#define	AR_RTS_OK	0x8088	/* MAC RTS exchange success counter */
#define	AR_RTS_FAIL	0x808c	/* MAC RTS exchange failure counter */
#define	AR_ACK_FAIL	0x8090	/* MAC ACK failure counter */
#define	AR_FCS_FAIL	0x8094	/* FCS check failure counter */
#define	AR_BEACON_CNT	0x8098	/* Valid beacon counter */

#define	AR_XRMODE	0x80c0	/* Extended range mode */
#define	AR_XRDEL	0x80c4	/* Extended range delay */
#define	AR_XRTO		0x80c8	/* Extended range timeout */
#define	AR_XRCRP	0x80cc	/* Extended range chirp */
#define	AR_XRSTMP	0x80d0	/* Extended range stomp */
#define	AR_SLEEP1	0x80d4	/* Enhanced sleep control 1 */
#define	AR_SLEEP2	0x80d8	/* Enhanced sleep control 2 */
#define	AR_SLEEP3	0x80dc	/* Enhanced sleep control 3 */
#define	AR_BSSMSKL	0x80e0	/* BSSID mask lower 32 bits */
#define	AR_BSSMSKU	0x80e4	/* BSSID mask upper 16 bits */
#define	AR_TPC		0x80e8	/* Transmit power control for self gen frames */
#define	AR_TFCNT	0x80ec	/* Profile count, transmit frames */
#define	AR_RFCNT	0x80f0	/* Profile count, receive frames */
#define	AR_RCCNT	0x80f4	/* Profile count, receive clear */
#define	AR_CCCNT	0x80f8	/* Profile count, cycle counter */

#define AR_QUIET1	0x80fc	/* Quiet time programming for TGh */
#define AR_QUIET1_NEXT_QUIET_S	0	/* TSF of next quiet period (TU) */
#define AR_QUIET1_NEXT_QUIET	0xffff
#define AR_QUIET1_QUIET_ENABLE	0x10000	/* Enable Quiet time operation */
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE	0x20000	/* Do we ack/cts during quiet period */

#define AR_QUIET2	0x8100	/* More Quiet time programming */
#define AR_QUIET2_QUIET_PER_S	0	/* Periodicity of quiet period (TU) */
#define AR_QUIET2_QUIET_PER	0xffff
#define AR_QUIET2_QUIET_DUR_S	16	/* Duration of quiet period (TU) */
#define AR_QUIET2_QUIET_DUR	0xffff0000

#define	AR_TSF_PARM	0x8104	/* TSF parameters */
#define AR_NOACK        0x8108  /* No ack policy in QoS Control Field */ 
#define	AR_PHY_ERR	0x810c	/* Phy error filter */

#define	AR_QOS_CONTROL	0x8118	/* Control TKIP MIC for QoS */
#define	AR_QOS_SELECT	0x811c	/* MIC QoS select */
#define	AR_MISC_MODE	0x8120	/* PCU Misc. mode control */

/* Hainan MIB counter registers */
#define	AR_FILTOFDM	0x8124	/* Count of filtered OFDM frames */
#define	AR_FILTCCK	0x8128	/* Count of filtered CCK frames */
#define	AR_PHYCNT1	0x812c	/* Phy Error 1 counter */
#define	AR_PHYCNTMASK1	0x8130	/* Phy Error 1 counter mask */
#define	AR_PHYCNT2	0x8134	/* Phy Error 2 counter */
#define	AR_PHYCNTMASK2	0x8138	/* Phy Error 2 counter mask */
#define	AR_PHY_COUNTMAX	(3 << 22)	/* Max value in counter before intr */
#define	AR_MIBCNT_INTRMASK (3<<22)	/* Mask for top two bits of counters */

#define	AR_RATE_DURATION_0	0x8700		/* base of multi-rate retry */
#define	AR_RATE_DURATION(_n)	(AR_RATE_DURATION_0 + ((_n)<<2))

#define	AR_KEYTABLE_0	0x8800	/* MAC Key Cache */
#define	AR_KEYTABLE(_n)	(AR_KEYTABLE_0 + ((_n)*32))

#define	AR_CFP_MASK	0x0000ffff /* Mask for next beacon time */

#define	AR_CR_RXE	0x00000004 /* Receive enable */
#define	AR_CR_RXD	0x00000020 /* Receive disable */
#define	AR_CR_SWI	0x00000040 /* One-shot software interrupt */

#define	AR_CFG_SWTD	0x00000001 /* byteswap tx descriptor words */
#define	AR_CFG_SWTB	0x00000002 /* byteswap tx data buffer words */
#define	AR_CFG_SWRD	0x00000004 /* byteswap rx descriptor words */
#define	AR_CFG_SWRB	0x00000008 /* byteswap rx data buffer words */
#define	AR_CFG_SWRG	0x00000010 /* byteswap register access data words */
#define	AR_CFG_AP_ADHOC_INDICATION	0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
#define	AR_CFG_PHOK	0x00000100 /* PHY OK status */
#define	AR_CFG_EEBS	0x00000200 /* EEPROM busy */
#define	AR_5211_CFG_CLK_GATE_DIS	0x00000400 /* Clock gating disable (Oahu only) */
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH	0x00060000 /* Mask of PCI core master request queue full threshold */
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17         /* Shift for PCI core master request queue full threshold */

#define	AR_IER_ENABLE	0x00000001 /* Global interrupt enable */
#define	AR_IER_DISABLE	0x00000000 /* Global interrupt disable */

#define	AR_DMASIZE_4B	0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
#define	AR_DMASIZE_8B	0x00000001 /* DMA size 8 bytes */
#define	AR_DMASIZE_16B	0x00000002 /* DMA size 16 bytes */
#define	AR_DMASIZE_32B	0x00000003 /* DMA size 32 bytes */
#define	AR_DMASIZE_64B	0x00000004 /* DMA size 64 bytes */
#define	AR_DMASIZE_128B	0x00000005 /* DMA size 128 bytes */
#define	AR_DMASIZE_256B	0x00000006 /* DMA size 256 bytes */
#define	AR_DMASIZE_512B	0x00000007 /* DMA size 512 bytes */

#define	AR_FTRIG	0x000003F0 /* Mask for Frame trigger level */
#define	AR_FTRIG_S	4          /* Shift for Frame trigger level */
#define	AR_FTRIG_IMMED	0x00000000 /* bytes in PCU TX FIFO before air */
#define	AR_FTRIG_64B	0x00000010 /* default */
#define	AR_FTRIG_128B	0x00000020
#define	AR_FTRIG_192B	0x00000030
#define	AR_FTRIG_256B	0x00000040 /* 5 bits total */

#define	AR_RXCFG_ZLFDMA	0x00000010 /* Enable DMA of zero-length frame */

#define	AR_MIBC_COW	0x00000001 /* counter overflow warning */
#define	AR_MIBC_FMC	0x00000002 /* freeze MIB counters */
#define	AR_MIBC_CMC	0x00000004 /* clear MIB counters */
#define	AR_MIBC_MCS	0x00000008 /* MIB counter strobe, increment all */

#define	AR_TOPS_MASK	0x0000FFFF /* Mask for timeout prescale */

#define	AR_RXNPTO_MASK	0x000003FF /* Mask for no frame received timeout */

#define	AR_TXNPTO_MASK	0x000003FF /* Mask for no frame transmitted timeout */
#define	AR_TXNPTO_QCU_MASK	0x000FFC00 /* Mask indicating the set of QCUs */
				 /* for which frame completions will cause */
				 /* a reset of the no frame xmit'd timeout */

#define	AR_RPGTO_MASK	0x000003FF /* Mask for receive frame gap timeout */

#define	AR_RPCNT_MASK	0x0000001F /* Mask for receive frame count limit */

#define	AR_MACMISC_DMA_OBS	0x000001E0 /* Mask for DMA observation bus mux select */
#define	AR_MACMISC_DMA_OBS_S	5          /* Shift for DMA observation bus mux select */
#define	AR_MACMISC_MISC_OBS	0x00000E00 /* Mask for MISC observation bus mux select */
#define	AR_MACMISC_MISC_OBS_S	9          /* Shift for MISC observation bus mux select */
#define	AR_MACMISC_MAC_OBS_BUS_LSB	0x00007000 /* Mask for MAC observation bus mux select (lsb) */
#define	AR_MACMISC_MAC_OBS_BUS_LSB_S	12         /* Shift for MAC observation bus mux select (lsb) */
#define	AR_MACMISC_MAC_OBS_BUS_MSB	0x00038000 /* Mask for MAC observation bus mux select (msb) */
#define	AR_MACMISC_MAC_OBS_BUS_MSB_S	15         /* Shift for MAC observation bus mux select (msb) */

/*
 * Interrupt Status Registers
 *
 * Only the bits in the ISR_P register and the IMR_P registers
 * control whether the MAC's INTA# output is asserted.  The bits in
 * the secondary interrupt status/mask registers control what bits
 * are set in the primary interrupt status register; however the
 * IMR_S* registers DO NOT determine whether INTA# is asserted.
 * That is INTA# is asserted only when the logical AND of ISR_P
 * and IMR_P is non-zero.  The secondary interrupt mask/status
 * registers affect what bits are set in ISR_P but they do not
 * directly affect whether INTA# is asserted.
 */
#define	AR_ISR_RXOK	0x00000001 /* At least one frame received sans errors */
#define	AR_ISR_RXDESC	0x00000002 /* Receive interrupt request */
#define	AR_ISR_RXERR	0x00000004 /* Receive error interrupt */
#define	AR_ISR_RXNOPKT	0x00000008 /* No frame received within timeout clock */
#define	AR_ISR_RXEOL	0x00000010 /* Received descriptor empty interrupt */
#define	AR_ISR_RXORN	0x00000020 /* Receive FIFO overrun interrupt */
#define	AR_ISR_TXOK	0x00000040 /* Transmit okay interrupt */
#define	AR_ISR_TXDESC	0x00000080 /* Transmit interrupt request */
#define	AR_ISR_TXERR	0x00000100 /* Transmit error interrupt */
#define	AR_ISR_TXNOPKT	0x00000200 /* No frame transmitted interrupt */
#define	AR_ISR_TXEOL	0x00000400 /* Transmit descriptor empty interrupt */
#define	AR_ISR_TXURN	0x00000800 /* Transmit FIFO underrun interrupt */
#define	AR_ISR_MIB	0x00001000 /* MIB interrupt - see MIBC */
#define	AR_ISR_SWI	0x00002000 /* Software interrupt */
#define	AR_ISR_RXPHY	0x00004000 /* PHY receive error interrupt */
#define	AR_ISR_RXKCM	0x00008000 /* Key-cache miss interrupt */
#define	AR_ISR_SWBA	0x00010000 /* Software beacon alert interrupt */
#define	AR_ISR_BRSSI	0x00020000 /* Beacon threshold interrupt */
#define	AR_ISR_BMISS	0x00040000 /* Beacon missed interrupt */
#define	AR_ISR_HIUERR	0x00080000 /* An unexpected bus error has occurred */
#define	AR_ISR_BNR	0x00100000 /* Beacon not ready interrupt */
#define	AR_ISR_RXCHIRP	0x00200000 /* Phy received a 'chirp' */
#define	AR_ISR_RXDOPPL	0x00400000 /* Phy received a 'doppler chirp' */
#define	AR_ISR_BCNMISC	0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO,
				      CABTO, DTIM bits from ISR_S2 */
#define	AR_ISR_TIM	0x00800000 /* TIM interrupt */
#define	AR_ISR_GPIO	0x01000000 /* GPIO Interrupt */
#define	AR_ISR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
#define	AR_ISR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
#define	AR_ISR_QTRIG	0x08000000 /* QCU scheduling trigger interrupt */
#define	AR_ISR_RESV0	0xF0000000 /* Reserved */

#define	AR_ISR_S0_QCU_TXOK	0x000003FF /* Mask for TXOK (QCU 0-9) */
#define AR_ISR_S0_QCU_TXOK_S	0
#define	AR_ISR_S0_QCU_TXDESC	0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
#define AR_ISR_S0_QCU_TXDESC_S	16

#define	AR_ISR_S1_QCU_TXERR	0x000003FF /* Mask for TXERR (QCU 0-9) */
#define AR_ISR_S1_QCU_TXERR_S	0
#define	AR_ISR_S1_QCU_TXEOL	0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
#define AR_ISR_S1_QCU_TXEOL_S	16

#define	AR_ISR_S2_QCU_TXURN	0x000003FF /* Mask for TXURN (QCU 0-9) */
#define	AR_ISR_S2_MCABT		0x00010000 /* Master cycle abort interrupt */
#define	AR_ISR_S2_SSERR		0x00020000 /* SERR interrupt */
#define	AR_ISR_S2_DPERR		0x00040000 /* PCI bus parity error */
#define	AR_ISR_S2_TIM		0x01000000 /* TIM */
#define	AR_ISR_S2_CABEND	0x02000000 /* CABEND */
#define	AR_ISR_S2_DTIMSYNC	0x04000000 /* DTIMSYNC */
#define	AR_ISR_S2_BCNTO		0x08000000 /* BCNTO */
#define	AR_ISR_S2_CABTO		0x10000000 /* CABTO */
#define	AR_ISR_S2_DTIM		0x20000000 /* DTIM */
#define	AR_ISR_S2_RESV0		0xE0F8FC00 /* Reserved */

#define	AR_ISR_S3_QCU_QCBROVF	0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define	AR_ISR_S3_QCU_QCBRURN	0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */

#define	AR_ISR_S4_QCU_QTRIG	0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define	AR_ISR_S4_RESV0		0xFFFFFC00 /* Reserved */

/*
 * Interrupt Mask Registers
 *
 * Only the bits in the IMR control whether the MAC's INTA#
 * output will be asserted.  The bits in the secondary interrupt
 * mask registers control what bits get set in the primary
 * interrupt status register; however the IMR_S* registers
 * DO NOT determine whether INTA# is asserted.
 */
#define	AR_IMR_RXOK	0x00000001 /* At least one frame received sans errors */
#define	AR_IMR_RXDESC	0x00000002 /* Receive interrupt request */
#define	AR_IMR_RXERR	0x00000004 /* Receive error interrupt */
#define	AR_IMR_RXNOPKT	0x00000008 /* No frame received within timeout clock */
#define	AR_IMR_RXEOL	0x00000010 /* Received descriptor empty interrupt */
#define	AR_IMR_RXORN	0x00000020 /* Receive FIFO overrun interrupt */
#define	AR_IMR_TXOK	0x00000040 /* Transmit okay interrupt */
#define	AR_IMR_TXDESC	0x00000080 /* Transmit interrupt request */
#define	AR_IMR_TXERR	0x00000100 /* Transmit error interrupt */
#define	AR_IMR_TXNOPKT	0x00000200 /* No frame transmitted interrupt */
#define	AR_IMR_TXEOL	0x00000400 /* Transmit descriptor empty interrupt */
#define	AR_IMR_TXURN	0x00000800 /* Transmit FIFO underrun interrupt */
#define	AR_IMR_MIB	0x00001000 /* MIB interrupt - see MIBC */
#define	AR_IMR_SWI	0x00002000 /* Software interrupt */
#define	AR_IMR_RXPHY	0x00004000 /* PHY receive error interrupt */
#define	AR_IMR_RXKCM	0x00008000 /* Key-cache miss interrupt */
#define	AR_IMR_SWBA	0x00010000 /* Software beacon alert interrupt */
#define	AR_IMR_BRSSI	0x00020000 /* Beacon threshold interrupt */
#define	AR_IMR_BMISS	0x00040000 /* Beacon missed interrupt */
#define	AR_IMR_HIUERR	0x00080000 /* An unexpected bus error has occurred */
#define	AR_IMR_BNR	0x00100000 /* BNR interrupt */
#define	AR_IMR_RXCHIRP	0x00200000 /* RXCHIRP interrupt */
#define	AR_IMR_BCNMISC	0x00800000 /* Venice: BCNMISC */
#define	AR_IMR_TIM	0x00800000 /* TIM interrupt */
#define	AR_IMR_GPIO	0x01000000 /* GPIO Interrupt */
#define	AR_IMR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
#define	AR_IMR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
#define	AR_IMR_QTRIG	0x08000000 /* QCU scheduling trigger interrupt */
#define	AR_IMR_RESV0	0xF0000000 /* Reserved */