ar5212reg.h

Atheros wifi driver source code

/*
 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2005 Atheros Communications, Inc.
 * All rights reserved.
 *
 * $Id: ar5212reg.h,v 1.1.1.1 2006/09/12 03:45:28 steven Exp $
 */
#ifndef _DEV_ATH_AR5212REG_H_
#define _DEV_ATH_AR5212REG_H_

/*
 * Definitions for the Atheros 5212 chipset.
 */

/* DMA Control and Interrupt Registers */
#define	AR_CR		0x0008	/* MAC control register */
#define	AR_RXDP		0x000C	/* MAC receive queue descriptor pointer */
#define	AR_CFG		0x0014	/* MAC configuration and status register */
#define	AR_IER		0x0024	/* MAC Interrupt enable register */
/* 0x28 is RTSD0 on the 5211 */
/* 0x2c is RTSD1 on the 5211 */
#define	AR_TXCFG	0x0030	/* MAC tx DMA size config register */
#define	AR_RXCFG	0x0034	/* MAC rx DMA size config register */
/* 0x38 is the jumbo descriptor address on the 5211 */
#define	AR_MIBC		0x0040	/* MAC MIB control register */
#define	AR_TOPS		0x0044	/* MAC timeout prescale count */
#define	AR_RXNPTO	0x0048	/* MAC no frame received timeout */
#define	AR_TXNPTO	0x004C	/* MAC no frame trasmitted timeout */
#define	AR_RPGTO	0x0050	/* MAC receive frame gap timeout */
#define	AR_RPCNT	0x0054	/* MAC receive frame count limit */
#define	AR_MACMISC	0x0058	/* MAC miscellaneous control/status register */
/* 0x5c is for QCU/DCU clock gating control on 5311 */
#define	AR_ISR		0x0080	/* MAC Primary interrupt status register */
#define	AR_ISR_S0	0x0084	/* MAC Secondary interrupt status register 0 */
#define	AR_ISR_S1	0x0088	/* MAC Secondary interrupt status register 1 */
#define	AR_ISR_S2	0x008c	/* MAC Secondary interrupt status register 2 */
#define	AR_ISR_S3	0x0090	/* MAC Secondary interrupt status register 3 */
#define	AR_ISR_S4	0x0094	/* MAC Secondary interrupt status register 4 */
#define	AR_IMR		0x00a0	/* MAC Primary interrupt mask register */
#define	AR_IMR_S0	0x00a4	/* MAC Secondary interrupt mask register 0 */
#define	AR_IMR_S1	0x00a8	/* MAC Secondary interrupt mask register 1 */
#define	AR_IMR_S2	0x00ac	/* MAC Secondary interrupt mask register 2 */
#define	AR_IMR_S3	0x00b0	/* MAC Secondary interrupt mask register 3 */
#define	AR_IMR_S4	0x00b4	/* MAC Secondary interrupt mask register 4 */
#define	AR_ISR_RAC	0x00c0	/* ISR read-and-clear access */
/* Shadow copies with read-and-clear access */
#define	AR_ISR_S0_S	0x00c4	/* ISR_S0 shadow copy */
#define	AR_ISR_S1_S	0x00c8	/* ISR_S1 shadow copy */
#define	AR_ISR_S2_S	0x00cc	/* ISR_S2 shadow copy */
#define	AR_ISR_S3_S	0x00d0	/* ISR_S3 shadow copy */
#define	AR_ISR_S4_S	0x00d4	/* ISR_S4 shadow copy */
#define	AR_DCM_A	0x0400	/* Decompression mask address */
#define	AR_DCM_D	0x0404	/* Decompression mask data */
#define	AR_DCCFG	0x0420	/* Decompression configuration */
#define	AR_CCFG		0x0600	/* Compression configuration */
#define	AR_CCUCFG	0x0604	/* Compression catchup configuration */
#define	AR_CPC_0	0x0610	/* Compression performance counter 0 */
#define	AR_CPC_1	0x0614	/* Compression performance counter 1 */
#define	AR_CPC_2	0x0618	/* Compression performance counter 2 */
#define	AR_CPC_3	0x061c	/* Compression performance counter 3 */
#define	AR_CPCOVF	0x0620	/* Compression performance overflow status */

#define	AR_Q0_TXDP	0x0800	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q1_TXDP	0x0804	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q2_TXDP	0x0808	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q3_TXDP	0x080c	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q4_TXDP	0x0810	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q5_TXDP	0x0814	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q6_TXDP	0x0818	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q7_TXDP	0x081c	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q8_TXDP	0x0820	/* MAC Transmit Queue descriptor pointer */
#define	AR_Q9_TXDP	0x0824	/* MAC Transmit Queue descriptor pointer */
#define	AR_QTXDP(_i)	(AR_Q0_TXDP + ((_i)<<2))

#define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
#define	AR_Q_TXD	0x0880	/* MAC Transmit Queue disable */

#define	AR_Q0_CBRCFG	0x08c0	/* MAC CBR configuration */
#define	AR_Q1_CBRCFG	0x08c4	/* MAC CBR configuration */
#define	AR_Q2_CBRCFG	0x08c8	/* MAC CBR configuration */
#define	AR_Q3_CBRCFG	0x08cc	/* MAC CBR configuration */
#define	AR_Q4_CBRCFG	0x08d0	/* MAC CBR configuration */
#define	AR_Q5_CBRCFG	0x08d4	/* MAC CBR configuration */
#define	AR_Q6_CBRCFG	0x08d8	/* MAC CBR configuration */
#define	AR_Q7_CBRCFG	0x08dc	/* MAC CBR configuration */
#define	AR_Q8_CBRCFG	0x08e0	/* MAC CBR configuration */
#define	AR_Q9_CBRCFG	0x08e4	/* MAC CBR configuration */
#define	AR_QCBRCFG(_i)	(AR_Q0_CBRCFG + ((_i)<<2))

#define	AR_Q0_RDYTIMECFG	0x0900	/* MAC ReadyTime configuration */
#define	AR_Q1_RDYTIMECFG	0x0904	/* MAC ReadyTime configuration */
#define	AR_Q2_RDYTIMECFG	0x0908	/* MAC ReadyTime configuration */
#define	AR_Q3_RDYTIMECFG	0x090c	/* MAC ReadyTime configuration */
#define	AR_Q4_RDYTIMECFG	0x0910	/* MAC ReadyTime configuration */
#define	AR_Q5_RDYTIMECFG	0x0914	/* MAC ReadyTime configuration */
#define	AR_Q6_RDYTIMECFG	0x0918	/* MAC ReadyTime configuration */
#define	AR_Q7_RDYTIMECFG	0x091c	/* MAC ReadyTime configuration */
#define	AR_Q8_RDYTIMECFG	0x0920	/* MAC ReadyTime configuration */
#define	AR_Q9_RDYTIMECFG	0x0924	/* MAC ReadyTime configuration */
#define	AR_QRDYTIMECFG(_i)	(AR_Q0_RDYTIMECFG + ((_i)<<2))

#define	AR_Q_ONESHOTARM_SC	0x0940	/* MAC OneShotArm set control */
#define	AR_Q_ONESHOTARM_CC	0x0980	/* MAC OneShotArm clear control */

#define	AR_Q0_MISC	0x09c0	/* MAC Miscellaneous QCU settings */
#define	AR_Q1_MISC	0x09c4	/* MAC Miscellaneous QCU settings */
#define	AR_Q2_MISC	0x09c8	/* MAC Miscellaneous QCU settings */
#define	AR_Q3_MISC	0x09cc	/* MAC Miscellaneous QCU settings */
#define	AR_Q4_MISC	0x09d0	/* MAC Miscellaneous QCU settings */
#define	AR_Q5_MISC	0x09d4	/* MAC Miscellaneous QCU settings */
#define	AR_Q6_MISC	0x09d8	/* MAC Miscellaneous QCU settings */
#define	AR_Q7_MISC	0x09dc	/* MAC Miscellaneous QCU settings */
#define	AR_Q8_MISC	0x09e0	/* MAC Miscellaneous QCU settings */
#define	AR_Q9_MISC	0x09e4	/* MAC Miscellaneous QCU settings */
#define	AR_QMISC(_i)	(AR_Q0_MISC + ((_i)<<2))

#define	AR_Q0_STS	0x0a00	/* MAC Miscellaneous QCU status */
#define	AR_Q1_STS	0x0a04	/* MAC Miscellaneous QCU status */
#define	AR_Q2_STS	0x0a08	/* MAC Miscellaneous QCU status */
#define	AR_Q3_STS	0x0a0c	/* MAC Miscellaneous QCU status */
#define	AR_Q4_STS	0x0a10	/* MAC Miscellaneous QCU status */
#define	AR_Q5_STS	0x0a14	/* MAC Miscellaneous QCU status */
#define	AR_Q6_STS	0x0a18	/* MAC Miscellaneous QCU status */
#define	AR_Q7_STS	0x0a1c	/* MAC Miscellaneous QCU status */
#define	AR_Q8_STS	0x0a20	/* MAC Miscellaneous QCU status */
#define	AR_Q9_STS	0x0a24	/* MAC Miscellaneous QCU status */
#define	AR_QSTS(_i)	(AR_Q0_STS + ((_i)<<2))

#define	AR_Q_RDYTIMESHDN	0x0a40	/* MAC ReadyTimeShutdown status */
#define	AR_Q_CBBS	0xb00	/* Compression buffer base select */
#define	AR_Q_CBBA	0xb04	/* Compression buffer base access */
#define	AR_Q_CBC	0xb08	/* Compression buffer configuration */

#define	AR_D0_QCUMASK	0x1000	/* MAC QCU Mask */
#define	AR_D1_QCUMASK	0x1004	/* MAC QCU Mask */
#define	AR_D2_QCUMASK	0x1008	/* MAC QCU Mask */
#define	AR_D3_QCUMASK	0x100c	/* MAC QCU Mask */
#define	AR_D4_QCUMASK	0x1010	/* MAC QCU Mask */
#define	AR_D5_QCUMASK	0x1014	/* MAC QCU Mask */
#define	AR_D6_QCUMASK	0x1018	/* MAC QCU Mask */
#define	AR_D7_QCUMASK	0x101c	/* MAC QCU Mask */
#define	AR_D8_QCUMASK	0x1020	/* MAC QCU Mask */
#define	AR_D9_QCUMASK	0x1024	/* MAC QCU Mask */
#define	AR_DQCUMASK(_i)	(AR_D0_QCUMASK + ((_i)<<2))

#define	AR_D0_LCL_IFS	0x1040	/* MAC DCU-specific IFS settings */
#define	AR_D1_LCL_IFS	0x1044	/* MAC DCU-specific IFS settings */
#define	AR_D2_LCL_IFS	0x1048	/* MAC DCU-specific IFS settings */
#define	AR_D3_LCL_IFS	0x104c	/* MAC DCU-specific IFS settings */
#define	AR_D4_LCL_IFS	0x1050	/* MAC DCU-specific IFS settings */
#define	AR_D5_LCL_IFS	0x1054	/* MAC DCU-specific IFS settings */
#define	AR_D6_LCL_IFS	0x1058	/* MAC DCU-specific IFS settings */
#define	AR_D7_LCL_IFS	0x105c	/* MAC DCU-specific IFS settings */
#define	AR_D8_LCL_IFS	0x1060	/* MAC DCU-specific IFS settings */
#define	AR_D9_LCL_IFS	0x1064	/* MAC DCU-specific IFS settings */
#define	AR_DLCL_IFS(_i)	(AR_D0_LCL_IFS + ((_i)<<2))

#define	AR_D0_RETRY_LIMIT	0x1080	/* MAC Retry limits */
#define	AR_D1_RETRY_LIMIT	0x1084	/* MAC Retry limits */
#define	AR_D2_RETRY_LIMIT	0x1088	/* MAC Retry limits */
#define	AR_D3_RETRY_LIMIT	0x108c	/* MAC Retry limits */
#define	AR_D4_RETRY_LIMIT	0x1090	/* MAC Retry limits */
#define	AR_D5_RETRY_LIMIT	0x1094	/* MAC Retry limits */
#define	AR_D6_RETRY_LIMIT	0x1098	/* MAC Retry limits */
#define	AR_D7_RETRY_LIMIT	0x109c	/* MAC Retry limits */
#define	AR_D8_RETRY_LIMIT	0x10a0	/* MAC Retry limits */
#define	AR_D9_RETRY_LIMIT	0x10a4	/* MAC Retry limits */
#define	AR_DRETRY_LIMIT(_i)	(AR_D0_RETRY_LIMIT + ((_i)<<2))

#define	AR_D0_CHNTIME	0x10c0	/* MAC ChannelTime settings */
#define	AR_D1_CHNTIME	0x10c4	/* MAC ChannelTime settings */
#define	AR_D2_CHNTIME	0x10c8	/* MAC ChannelTime settings */
#define	AR_D3_CHNTIME	0x10cc	/* MAC ChannelTime settings */
#define	AR_D4_CHNTIME	0x10d0	/* MAC ChannelTime settings */
#define	AR_D5_CHNTIME	0x10d4	/* MAC ChannelTime settings */
#define	AR_D6_CHNTIME	0x10d8	/* MAC ChannelTime settings */
#define	AR_D7_CHNTIME	0x10dc	/* MAC ChannelTime settings */
#define	AR_D8_CHNTIME	0x10e0	/* MAC ChannelTime settings */
#define	AR_D9_CHNTIME	0x10e4	/* MAC ChannelTime settings */
#define	AR_DCHNTIME(_i)	(AR_D0_CHNTIME + ((_i)<<2))

#define	AR_D0_MISC	0x1100	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D1_MISC	0x1104	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D2_MISC	0x1108	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D3_MISC	0x110c	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D4_MISC	0x1110	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D5_MISC	0x1114	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D6_MISC	0x1118	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D7_MISC	0x111c	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D8_MISC	0x1120	/* MAC Miscellaneous DCU-specific settings */
#define	AR_D9_MISC	0x1124	/* MAC Miscellaneous DCU-specific settings */
#define	AR_DMISC(_i)	(AR_D0_MISC + ((_i)<<2))

#define	AR_D_SEQNUM	0x1140	/* MAC Frame sequence number */

/* MAC DCU-global IFS settings */
#define	AR_D_GBL_IFS_SIFS	0x1030	/* DCU global SIFS settings */
#define	AR_D_GBL_IFS_SLOT	0x1070	/* DC global slot interval */
#define	AR_D_GBL_IFS_EIFS	0x10b0	/* DCU global EIFS setting */
#define	AR_D_GBL_IFS_MISC	0x10f0	/* DCU global misc. IFS settings */
#define	AR_D_FPCTL	0x1230		/* DCU frame prefetch settings */
#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */
#define	AR_D_TXBLK_CMD	0x1038		/* DCU transmit filter cmd (w/only) */
#define	AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))	/* DCU transmit filter data */
#define	AR_D_TXBLK_CLR	0x143c		/* DCU clear tx filter (w/only) */
#define	AR_D_TXBLK_SET	0x147c		/* DCU set tx filter (w/only) */

#define	AR_RC		0x4000	/* Warm reset control register */
#define	AR_SCR		0x4004	/* Sleep control register */
#define	AR_INTPEND	0x4008	/* Interrupt Pending register */
#define	AR_SFR		0x400C	/* Sleep force register */
#define	AR_PCICFG	0x4010	/* PCI configuration register */
#define	AR_GPIOCR	0x4014	/* GPIO control register */
#define	AR_GPIODO	0x4018	/* GPIO data output access register */
#define	AR_GPIODI	0x401C	/* GPIO data input access register */
#define	AR_SREV		0x4020	/* Silicon Revision register */
#define	AR_TXEPOST	0x4028	/* TXE write posting resgister */
#define	AR_QSM		0x402C	/* QCU sleep mask */

#define AR_PCIE_SERDES	0x4080  /* PCIe Serdes register */
#define AR_PCIE_SERDES2	0x4084  /* PCIe Serdes register */

#define	AR_EEPROM_ADDR	0x6000	/* EEPROM address register (10 bit) */
#define	AR_EEPROM_DATA	0x6004	/* EEPROM data register (16 bit) */
#define	AR_EEPROM_CMD	0x6008	/* EEPROM command register */
#define	AR_EEPROM_STS	0x600c	/* EEPROM status register */
#define	AR_EEPROM_CFG	0x6010	/* EEPROM configuration register */

#define	AR_STA_ID0	0x8000	/* MAC station ID0 register - low 32 bits */
#define	AR_STA_ID1	0x8004	/* MAC station ID1 register - upper 16 bits */
#define	AR_BSS_ID0	0x8008	/* MAC BSSID low 32 bits */
#define	AR_BSS_ID1	0x800C	/* MAC BSSID upper 16 bits / AID */
#define	AR_SLOT_TIME	0x8010	/* MAC Time-out after a collision */
#define	AR_TIME_OUT	0x8014	/* MAC ACK & CTS time-out */
#define	AR_RSSI_THR	0x8018	/* MAC RSSI warning & missed beacon threshold */
#define	AR_USEC		0x801c	/* MAC transmit latency register */
#define	AR_BEACON	0x8020	/* MAC beacon control value/mode bits */
#define	AR_CFP_PERIOD	0x8024	/* MAC CFP Interval (TU/msec) */
#define	AR_TIMER0	0x8028	/* MAC Next beacon time (TU/msec) */
#define	AR_TIMER1	0x802c	/* MAC DMA beacon alert time (1/8 TU) */
#define	AR_TIMER2	0x8030	/* MAC Software beacon alert (1/8 TU) */
#define	AR_TIMER3	0x8034	/* MAC ATIM window time */
#define	AR_CFP_DUR	0x8038	/* MAC maximum CFP duration in TU */
#define	AR_RX_FILTER	0x803C	/* MAC receive filter register */
#define	AR_MCAST_FIL0	0x8040	/* MAC multicast filter lower 32 bits */
#define	AR_MCAST_FIL1	0x8044	/* MAC multicast filter upper 32 bits */
#define	AR_DIAG_SW	0x8048	/* MAC PCU control register */