ar5210.h

Atheros wifi driver source code

/*
 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2005 Atheros Communications, Inc.
 * All rights reserved.
 *
 * $Id: ar5210.h,v 1.1.1.1 2006/09/12 03:45:22 steven Exp $
 */
#ifndef _ATH_AR5210_H_
#define _ATH_AR5210_H_

#define	AR5210_MAGIC	0x19980124

#if 0
/*
 * RTS_ENABLE includes LONG_PKT because they essentially
 * imply the same thing, and are set or not set together
 * for this chip
 */
#define AR5210_TXD_CTRL_A_HDR_LEN(_val)         (((_val)      ) & 0x0003f)
#define AR5210_TXD_CTRL_A_TX_RATE(_val)         (((_val) <<  6) & 0x003c0)
#define AR5210_TXD_CTRL_A_RTS_ENABLE            (                 0x00c00)
#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
#define AR5210_TXD_CTRL_A_ANT_MODE(_val)        (((_val) << 13) & 0x02000)
#define AR5210_TXD_CTRL_A_PKT_TYPE(_val)        (((_val) << 14) & 0x1c000)
#define AR5210_TXD_CTRL_A_INT_REQ               (                 0x20000)
#define AR5210_TXD_CTRL_A_KEY_VALID             (                 0x40000)
#define AR5210_TXD_CTRL_B_KEY_ID(_val)          (((_val)      ) & 0x0003f)
#define AR5210_TXD_CTRL_B_RTS_DURATION(_val)    (((_val) <<  6) & 0x7ffc0)
#endif

#define INIT_CONFIG_STATUS              0x00000000
#define INIT_ACKTOPS                    0x00000008
#define INIT_BCON_CNTRL_REG             0x00000000
#define INIT_SLOT_TIME                  0x00000168
#define INIT_SLOT_TIME_TURBO            0x000001e0 /* More aggressive turbo slot timing = 6 us */
#define INIT_ACK_CTS_TIMEOUT            0x04000400
#define INIT_ACK_CTS_TIMEOUT_TURBO      0x08000800

#define INIT_USEC                       0x27
#define INIT_USEC_TURBO                 0x4f
#define INIT_USEC_32                    0x1f
#define INIT_TX_LATENCY                 0x36
#define INIT_RX_LATENCY                 0x1D
#define INIT_TRANSMIT_LATENCY \
	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
	 (INIT_USEC_32 << 7) | INIT_USEC )
#define INIT_TRANSMIT_LATENCY_TURBO  \
	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
	 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)

#define INIT_SIFS                       0x230 /* = 16 us - 2 us */
#define INIT_SIFS_TURBO                 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */

/*
 * Various fifo fill before Tx start, in 64-byte units
 * i.e. put the frame in the air while still DMAing
 */
#define MIN_TX_FIFO_THRESHOLD           0x1
#define MAX_TX_FIFO_THRESHOLD           ((IEEE80211_MAX_LEN / 64) + 1)

#define INIT_NEXT_CFP_START             0xffffffff

#define INIT_BEACON_PERIOD              0xffff
#define INIT_BEACON_EN                  0 /* this should be set by AP only when it's ready */
#define INIT_BEACON_CONTROL \
	((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
	 (INIT_TIM_OFFSET<<16)  | INIT_BEACON_PERIOD)

#define INIT_RSSI_THR                   0x00000700 /* Missed beacon counter initialized to max value of 7 */
#define INIT_ProgIFS                    0x398      /* PIFS - 2us */
#define INIT_ProgIFS_TURBO              0x3C0
#define INIT_EIFS                       0xd70
#define INIT_EIFS_TURBO                 0x1ae0
#define INIT_CARR_SENSE_EN              1
#define INIT_PROTO_TIME_CNTRL           ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
                                          (INIT_ProgIFS) )
#define INIT_PROTO_TIME_CNTRL_TURBO     ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
                                          (INIT_ProgIFS_TURBO) )

/*
 * EEPROM defines for Version 1 Crete EEPROM.
 *
 * The EEPROM is segmented into three sections:
 *
 *    PCI/Cardbus default configuration settings
 *    Cardbus CIS tuples and vendor-specific data
 *    Atheros-specific data
 *
 * EEPROM entries are read 32-bits at a time through the PCI bus
 * interface but are all 16-bit values.
 *
 * Access to the Atheros-specific data is controlled by protection
 * bits and the data is checksum'd.  The driver reads the Atheros
 * data from the EEPROM at attach and caches it in its private state.
 * This data includes the local regulatory domain, channel calibration
 * settings, and phy-related configuration settings.
 */
#define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
#define	AR_EEPROM_MAGIC		0x3d	/* magic number */
#define AR_EEPROM_PROTECT	0x3f	/* Atheros segment protect register */
#define	AR_EEPROM_PROTOTECT_WP_128_191	0x80
#define AR_EEPROM_REG_DOMAIN	0xbf	/* Current regulatory domain register */
#define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
#define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
#define	AR_EEPROM_ATHEROS(n)	(AR_EEPROM_ATHEROS_BASE+(n))
#define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
#define AR_EEPROM_ATHEROS_TP_SETTINGS	0x09	/* Transmit power settings */
#define AR_REG_DOMAINS_MAX	4	/* # of Regulatory Domains */
#define AR_CHANNELS_MAX		5	/* # of Channel calibration groups */
#define AR_TP_SETTINGS_SIZE	11	/* # locations/Channel group */
#define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */

#define AR_I2DBM(x)	((u_int8_t)((x * 2) + 3))

/*
 * Transmit power and channel calibration settings.
 */
struct tpcMap {
	u_int8_t	pcdac[AR_TP_SCALING_ENTRIES];
	u_int8_t	gainF[AR_TP_SCALING_ENTRIES];
	u_int8_t	rate36;
	u_int8_t	rate48;
	u_int8_t	rate54;
	u_int8_t	regdmn[AR_REG_DOMAINS_MAX];
};

/* NB: this is in ah_eeprom.h which isn't used for 5210 support */
#ifndef MAX_RATE_POWER
#define	MAX_RATE_POWER	60
#endif

#undef HAL_NUM_TX_QUEUES	/* from ah.h */
#define	HAL_NUM_TX_QUEUES	3

struct ath_hal_5210 {
	struct ath_hal_private ah_priv;	/* base definitions */

	/*
	 * Information retrieved from EEPROM
	 */
	u_int16_t	ah_eeversion;		/* EEPROM Version field */
	u_int16_t	ah_eeprotect;		/* EEPROM protection settings */
	u_int16_t	ah_antenna;		/* Antenna Settings */
	u_int16_t	ah_biasCurrents;	/* OB, DB */
	u_int8_t	ah_thresh62;		/* thresh62 */
	u_int8_t	ah_xlnaOn;		/* External LNA timing */
	u_int8_t	ah_xpaOff;		/* Extern output stage timing */
	u_int8_t	ah_xpaOn;		/* Extern output stage timing */
	u_int8_t	ah_rfKill;		/* Single low bit signalling if RF Kill is implemented */
	u_int8_t	ah_devType;		/* Type: PCI, miniPCI, CB */
	u_int8_t	ah_regDomain[AR_REG_DOMAINS_MAX];
						/* calibrated reg domains */
	struct tpcMap	ah_tpc[AR_CHANNELS_MAX];
	u_int8_t	ah_macaddr[IEEE80211_ADDR_LEN];
	/*
	 * Runtime state.
	 */
	u_int32_t	ah_maskReg;		/* shadow of IMR+IER regs */
	u_int32_t	ah_txOkInterruptMask;
	u_int32_t	ah_txErrInterruptMask;
	u_int32_t	ah_txDescInterruptMask;
	u_int32_t	ah_txEolInterruptMask;
	u_int32_t	ah_txUrnInterruptMask;
	HAL_POWER_MODE	ah_powerMode;
	u_int8_t	ah_bssid[IEEE80211_ADDR_LEN];
	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
	/*
	 * Station mode support.