ar5210_reset.c

Atheros wifi driver source code

	/* Wait for AGC changes to be enacted */
	OS_DELAY(20);

	/*
	 * We disable RF mix/gain stages for the PGA to avoid a
	 * race condition that will occur with receiving a frame
	 * and performing the AGC calibration.  This will be
	 * re-enabled at the end of offset cal.  We turn off AGC
	 * writes during this write as it will go over the analog bus.
	 */
	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
	OS_DELAY(10);		 /* wait for the AGC traffic to cease */
	OS_REG_WRITE(ah, 0x98D4, 0x21);
	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));

	/* wait to make sure that additional AGC traffic has quiesced */
	OS_DELAY(1000);

	/* AGC calibration (this was added to make the NF threshold check work) */
	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
		 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0))
		HALDEBUG(ah, "%s: AGC calibration timeout\n", __func__);

	/* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
	OS_REG_WRITE(ah, 0x9858, reg9858);
	OS_REG_WRITE(ah, 0x985c, reg985c);
	OS_REG_WRITE(ah, 0x9868, reg9868);

	/* Perform noise floor and set status */
	if (!ar5210CalNoiseFloor(ah, chan)) {
		/*
		 * Delay 5ms before retrying the noise floor -
		 * just to make sure.  We're in an error
		 * condition here
		 */
		HALDEBUG(ah, "%s: Performing 2nd Noise Cal\n", __func__);
		OS_DELAY(5000);
		if (!ar5210CalNoiseFloor(ah, chan))
			chan->channelFlags |= CHANNEL_CW_INT;
	}

	/* Clear tx and rx disable bit */
	OS_REG_WRITE(ah, AR_DIAG_SW,
		 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));

	/* Re-enable Beacons */
	OS_REG_WRITE(ah, AR_BEACON, regBeacon);

	*isIQdone = AH_TRUE;

	return AH_TRUE;
}

/*
 * Writes the given reset bit mask into the reset register
 */
static HAL_BOOL
ar5210SetResetReg(struct ath_hal *ah, u_int32_t resetMask, u_int delay)
{
	u_int32_t mask = resetMask ? resetMask : ~0;
	HAL_BOOL rt;

	OS_REG_WRITE(ah, AR_RC, resetMask);
	/* need to wait at least 128 clocks when reseting PCI before read */
	OS_DELAY(delay);

	resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
	mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
	rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
        if ((resetMask & AR_RC_RMAC) == 0) {
		if (isBigEndian()) {
			/*
			 * Set CFG, little-endian for register
			 * and descriptor accesses.
			 */
			mask = INIT_CONFIG_STATUS |
				AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
			OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
		} else
			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
	}
	return rt;
}


/*
 * Returns: the pcdac value
 */
static u_int8_t
getPcdac(struct ath_hal *ah, struct tpcMap *pRD, u_int8_t dBm)
{
	int32_t	 i;
	int useNextEntry = AH_FALSE;
	u_int32_t interp;

	for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) {
		/* Check for exact entry */
		if (dBm == AR_I2DBM(i)) {
			if (pRD->pcdac[i] != 63)
				return pRD->pcdac[i];
			useNextEntry = AH_TRUE;
		} else if (dBm + 1 == AR_I2DBM(i) && i > 0) {
			/* Interpolate for between entry with a logish scale */
			if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) {
				interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999;
				interp = (interp / 1000) + pRD->pcdac[i-1];
				return interp;
			}
			useNextEntry = AH_TRUE;
		} else if (useNextEntry == AH_TRUE) {
			/* Grab the next lowest */
			if (pRD->pcdac[i] != 63)
				return pRD->pcdac[i];
		}
	}

	/* Return the lowest Entry if we haven't returned */
	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++)
		if (pRD->pcdac[i] != 63)
			return pRD->pcdac[i];

	/* No value to return from table */
#ifdef AH_DEBUG
	ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);
#endif
	return 1;
}

/*
 * Find or interpolates the gainF value from the table ptr.
 */
static u_int8_t
getGainF(struct ath_hal *ah, struct tpcMap *pRD, u_int8_t pcdac, u_int8_t *dBm)
{
	u_int32_t interp;
	int low, high, i;

	low = high = -1;

	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) {
		if(pRD->pcdac[i] == 63)
			continue;
		if (pcdac == pRD->pcdac[i]) {
			*dBm = AR_I2DBM(i);
			return pRD->gainF[i];  /* Exact Match */
		}
		if (pcdac > pRD->pcdac[i])
			low = i;
		if (pcdac < pRD->pcdac[i]) {
			high = i;
			if (low == -1) {
				*dBm = AR_I2DBM(i);
				/* PCDAC is lower than lowest setting */
				return pRD->gainF[i];
			}
			break;
		}
	}
	if (i >= AR_TP_SCALING_ENTRIES && low == -1) {
		/* No settings were found */
#ifdef AH_DEBUG
		ath_hal_printf(ah,
			"%s: no valid entries in the pcdac table: %d\n",
			__func__, pcdac);
#endif
		return 63;
	}
	if (i >= AR_TP_SCALING_ENTRIES) {
		/* PCDAC setting was above the max setting in the table */
		*dBm = AR_I2DBM(low);
		return pRD->gainF[low];
	}
	/* Only exact if table has no missing entries */
	*dBm = (low + high) + 3;

	/*
	 * Perform interpolation between low and high values to find gainF
	 * linearly scale the pcdac between low and high
	 */
	interp = ((pcdac - pRD->pcdac[low]) * 1000) /
		  (pRD->pcdac[high] - pRD->pcdac[low]);
	/*
	 * Multiply the scale ratio by the gainF difference
	 * (plus a rnd up factor)
	 */
	interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000;

	/* Add ratioed gain_f to low gain_f value */
	return interp + pRD->gainF[low];
}

HAL_BOOL
ar5210SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit)
{
	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
	/* XXX flush to h/w */
	return AH_TRUE;
}

/*
 * Get TXPower values and set them in the radio
 */
static HAL_BOOL
setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, u_int8_t cp[17])
{
	struct ath_hal_5210 *ahp = AH5210(ah);
	u_int8_t gainFRD, gainF36, gainF48, gainF54;
	u_int8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
	u_int32_t rd, group;
	struct tpcMap  *pRD;

	/* Set OB/DB Values regardless of channel */
	cp[15] = (ahp->ah_biasCurrents >> 4) & 0x7;
	cp[16] = ahp->ah_biasCurrents & 0x7;

	if (chan->channel < 5170 || chan->channel > 5320) {
		HALDEBUG(ah, "%s: invalid channel %u\n",
			__func__, chan->channel);
		return AH_FALSE;
	}

	HALASSERT(ahp->ah_eeversion == 1);

	/* Match regulatory domain */
	for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++)
		if (AH_PRIVATE(ah)->ah_currentRD == ahp->ah_regDomain[rd])
			break;
	if (rd == AR_REG_DOMAINS_MAX) {
#ifdef AH_DEBUG
		ath_hal_printf(ah,
			"%s: no calibrated regulatory domain matches the "
			"current regularly domain (0x%0x)\n", __func__, rd);
#endif
		return AH_FALSE;
	}
	group = ((chan->channel - 5170) / 10);

	if (group > 11) {
		/* Pull 5.29 into the 5.27 group */
		group--;
	}

	/* Integer divide will set group from 0 to 4 */
	group = group / 3;
	pRD   = &ahp->ah_tpc[group];

	/* Set PC DAC Values */
	cp[14] = pRD->regdmn[rd];
	cp[9]  = AH_MIN(pRD->regdmn[rd], pRD->rate36);
	cp[8]  = AH_MIN(pRD->regdmn[rd], pRD->rate48);
	cp[7]  = AH_MIN(pRD->regdmn[rd], pRD->rate54);

	/* Find Corresponding gainF values for RD, 36, 48, 54 */
	gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);
	gainF36 = getGainF(ah, pRD, cp[9], &dBm36);
	gainF48 = getGainF(ah, pRD, cp[8], &dBm48);
	gainF54 = getGainF(ah, pRD, cp[7], &dBm54);

	/* Power Scale if requested */
	if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
		static const u_int16_t tpcScaleReductionTable[5] =
			{ 0, 3, 6, 9, MAX_RATE_POWER };
		u_int16_t tpScale;

		tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
		if (dBmRD < tpScale+3)
			dBmRD = 3;		/* min */
		else
			dBmRD -= tpScale;
		cp[14]  = getPcdac(ah, pRD, dBmRD);
		gainFRD = getGainF(ah, pRD, cp[14], &dontcare);
		dBm36   = AH_MIN(dBm36, dBmRD);
		cp[9]   = getPcdac(ah, pRD, dBm36);
		gainF36 = getGainF(ah, pRD, cp[9], &dontcare);
		dBm48   = AH_MIN(dBm48, dBmRD);
		cp[8]   = getPcdac(ah, pRD, dBm48);
		gainF48 = getGainF(ah, pRD, cp[8], &dontcare);
		dBm54   = AH_MIN(dBm54, dBmRD);
		cp[7]   = getPcdac(ah, pRD, dBm54);
		gainF54 = getGainF(ah, pRD, cp[7], &dontcare);
	}
	/* Record current dBm at rate 6 */
	AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;

	cp[13] = cp[12] = cp[11] = cp[10] = cp[14];

	/* Set GainF Values */
	cp[0] = gainFRD - gainF54;
	cp[1] = gainFRD - gainF48;
	cp[2] = gainFRD - gainF36;
	/* 9, 12, 18, 24 have no gain_delta from 6 */
	cp[3] = cp[4] = cp[5] = cp[6] = 0;
	return AH_TRUE;
}

/*
 * Places the device in and out of reset and then places sane
 * values in the registers based on EEPROM config, initialization
 * vectors (as determined by the mode), and station configuration
 */
HAL_BOOL
ar5210SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
{
#define	N(a)	(sizeof (a) / sizeof (a[0]))
	static const u_int32_t pwr_regs_start[17] = {
		0x00000000, 0x00000000, 0x00000000,
		0x00000000, 0x00000000, 0xf0000000,
		0xcc000000, 0x00000000, 0x00000000,
		0x00000000, 0x0a000000, 0x000000e2,
		0x0a000020, 0x01000002, 0x01000018,
		0x40000000, 0x00000418
	};
	u_int16_t i;
	u_int8_t cp[sizeof(ar5k0007_pwrSettings)];
	u_int32_t pwr_regs[17];

	OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs));
	OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp));

	/* Check the EEPROM tx power calibration settings */
	if (!setupPowerSettings(ah, chan, cp)) {
#ifdef AH_DEBUG
		ath_hal_printf(ah, "%s: unable to setup power settings\n",
			__func__);
#endif
		return AH_FALSE;
	}
	if (cp[15] < 1 || cp[15] > 5) {
#ifdef AH_DEBUG
		ath_hal_printf(ah, "%s: OB out of range (%u)\n",
			__func__, cp[15]);
#endif
		return AH_FALSE;
	}
	if (cp[16] < 1 || cp[16] > 5) {
#ifdef AH_DEBUG
		ath_hal_printf(ah, "%s: DB out of range (%u)\n",
			__func__, cp[16]);
#endif
		return AH_FALSE;
	}

	/* reverse bits of the transmit power array */
	for (i = 0; i < 7; i++)
		cp[i] = ath_hal_reverseBits(cp[i], 5);
	for (i = 7; i < 15; i++)
		cp[i] = ath_hal_reverseBits(cp[i], 6);

	/* merge transmit power values into the register - quite gross */
	pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
	pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) | 
			((cp[1] >> 3) & 0x03);
	pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
	pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
		       ((cp[4] >> 4) & 0x01);
	pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
	pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
			((cp[7] >> 5) & 0x01);
	pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
	pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
	pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
	pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
	pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
	pwr_regs[11] |= ((cp[14] >> 5) & 0x01);

	/* Set OB */
	pwr_regs[8] |=  (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80;
	pwr_regs[9] |=  (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03;

	/* Set DB */
	pwr_regs[9] |=  (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C;

	/* Write the registers */
	for (i = 0; i < N(pwr_regs)-1; i++)
		OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);
	/* last write is a flush */
	OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);

	return AH_TRUE;
#undef N
}

/*
 * Takes the MHz channel value and sets the Channel value
 *
 * ASSUMES: Writes enabled to analog bus before AGC is active
 *   or by disabling the AGC.
 */
static HAL_BOOL
ar5210SetChannel(struct ath_hal *ah, HAL_CHANNEL *chan)
{
	HAL_CHANNEL_INTERNAL *ichan;
	u_int32_t data;

	ichan = ath_hal_checkchannel(ah, chan);
	if (ichan == AH_NULL) {
		HALDEBUG(ah, "%s: invalid channel %u MHz flags 0x%x\n",
			__func__, chan->channel, chan->channelFlags);
		return AH_FALSE;
	}
	/* Set the Channel */
	data = ath_hal_reverseBits((chan->channel - 5120)/10, 5);
	data = (data << 1) | 0x41;
	OS_REG_WRITE(ah, AR_PHY(0x27), data);
	OS_REG_WRITE(ah, AR_PHY(0x30), 0);
	AH_PRIVATE(ah)->ah_curchan = ichan;	
	return AH_TRUE;
}

int16_t
ar5210GetNoiseFloor(struct ath_hal *ah)
{
	int16_t nf;

	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
	if (nf & 0x100)
		nf = 0 - ((nf ^ 0x1ff) + 1);
	return nf;
}

#define NORMAL_NF_THRESH (-72)
/*
 * Peform the noisefloor calibration and check for
 * any constant channel interference
 *
 * Returns: TRUE for a successful noise floor calibration; else FALSE
 */
HAL_BOOL
ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL *chan)
{
	int32_t nf, nfLoops;

	/* Calibrate the noise floor */
	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
		OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);

	/* Do not read noise floor until it has done the first update */
	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {
#ifdef ATH_HAL_DEBUG
		ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",
			OS_REG_READ(ah, AR_PHY_AGCCTL));
		ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",
			OS_REG_READ(ah, AR_RC));
		ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",
			OS_REG_READ(ah, AR_PHY_ACTIVE));
#endif /* ATH_HAL_DEBUG */
		return AH_FALSE;
	}

	nf = 0;
	/* Keep checking until the floor is below the threshold or the nf is done */
	for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) {
		OS_DELAY(1000); /* Sleep for 1 ms */
		nf = ar5210GetNoiseFloor(ah);
	}

	if (nf > NORMAL_NF_THRESH) {
		HALDEBUG(ah, "%s: Bad noise cal %d\n", __func__, nf);
		return AH_FALSE;
	}
	return AH_TRUE;
}

HAL_RFGAIN
ar5210GetRfgain(struct ath_hal *ah)
{
	return HAL_RFGAIN_INACTIVE;
}
#endif /* AH_SUPPORT_AR5210 */