ar5210reg.h

Atheros wifi driver source code

#define	AR_TXCFG_SDMAMR		0x00000007	/* DMA burst size 2^(2+x) */
#define	AR_TXCFG_TXFSTP		0x00000008	/* Stop TX DMA on filtered */
#define	AR_TXCFG_TXFULL		0x00000070	/* TX DMA desc Q full thresh */
#define	AR_TXCFG_TXCONT_EN	0x00000080	/* Enable continuous TX mode */
#define	AR_TXCFG_BITS	"\20\3TXFSTP\7TXCONT_EN"

#define	AR_RXCFG_SDMAMW		0x00000007	/* DMA burst size 2^(2+x) */
#define	AR_RXCFG_ZLFDMA		0x00000010	/* enable zero length DMA */

/* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */
#define	AR_DMASIZE_4B		0		/* DMA size 4 bytes */
#define	AR_DMASIZE_8B		1		/* DMA size 8 bytes */
#define	AR_DMASIZE_16B		2		/* DMA size 16 bytes */
#define	AR_DMASIZE_32B		3		/* DMA size 32 bytes */
#define	AR_DMASIZE_64B		4		/* DMA size 64 bytes */
#define	AR_DMASIZE_128B		5		/* DMA size 128 bytes */
#define	AR_DMASIZE_256B		6		/* DMA size 256 bytes */
#define	AR_DMASIZE_512B		7		/* DMA size 512 bytes */

#define	AR_MIBC_COW		0x00000001	/* counter overflow warning */
#define	AR_MIBC_FMC		0x00000002	/* freeze MIB counters */
#define	AR_MIBC_CMC		0x00000004	/* clear MIB counters */
#define	AR_MIBC_MCS		0x00000008	/* MIB counter strobe */

#define	AR_RFCNT_RFCL		0x0000000f	/* RX frame count limit */

#define	AR_MISC_LED_DECAY	0x001c0000	/* LED decay rate */
#define	AR_MISC_LED_BLINK	0x00e00000	/* LED blink rate */

#define	AR_RC_RPCU		0x00000001	/* PCU Warm Reset */
#define	AR_RC_RDMA		0x00000002	/* DMA Warm Reset */
#define	AR_RC_RMAC		0x00000004	/* MAC Warm Reset */
#define	AR_RC_RPHY		0x00000008	/* PHY Warm Reset */
#define	AR_RC_RPCI		0x00000010	/* PCI Core Warm Reset */
#define	AR_RC_BITS	"\20\1RPCU\2RDMA\3RMAC\4RPHY\5RPCI"

#define	AR_SCR_SLDUR		0x0000ffff	/* sleep duration */
#define	AR_SCR_SLE		0x00030000	/* sleep enable */
#define	AR_SCR_SLE_S		16
#define	AR_SCR_SLE_WAKE		0x00000000	/* force wake */
#define	AR_SCR_SLE_SLP		0x00010000	/* force sleep */
#define	AR_SCR_SLE_ALLOW	0x00020000	/* allow to control sleep */
#define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE_ALLOW"

#define	AR_INTPEND_IP		0x00000001	/* interrupt pending */
#define	AR_INTPEND_BITS	"\20\1IP"

#define	AR_SFR_SF		0x00000001	/* force sleep immediately */

#define	AR_PCICFG_EEPROMSEL	0x00000001	/* EEPROM access enable */
#define	AR_PCICFG_CLKRUNEN	0x00000004	/* CLKRUN enable */
#define	AR_PCICFG_LED_PEND	0x00000020	/* LED for assoc pending */
#define	AR_PCICFG_LED_ACT	0x00000040	/* LED for assoc active */
#define	AR_PCICFG_SL_INTEN	0x00000800	/* Enable sleep intr */
#define	AR_PCICFG_LED_BCTL	0x00001000	/* LED blink for local act */
#define	AR_PCICFG_SL_INPEN	0x00002800	/* sleep even intr pending */
#define	AR_PCICFG_SPWR_DN	0x00010000	/* sleep indication */
#define	AR_PCICFG_BITS \
	"\20\1EEPROMSEL\3CLKRUNEN\5LED_PEND\6LED_ACT\13SL_INTEN"\
	"\14LED_BCTL\20SPWR_DN"

#define	AR_GPIOCR_IN(n)		(0<<((n)*2))	/* input-only */
#define	AR_GPIOCR_OUT0(n)	(1<<((n)*2))	/* output-only if GPIODO = 0 */
#define	AR_GPIOCR_OUT1(n)	(2<<((n)*2))	/* output-only if GPIODO = 1 */
#define	AR_GPIOCR_OUT(n)	(3<<((n)*2))	/* always output */
#define	AR_GPIOCR_ALL(n)	(3<<((n)*2))	/* all bits for pin */
#define	AR_GPIOCR_INT_SEL(n)	((n)<<12)	/* GPIO interrupt pin select */
#define	AR_GPIOCR_INT_ENA	0x00008000	/* Enable GPIO interrupt */
#define	AR_GPIOCR_INT_SELL	0x00000000	/* Interrupt if pin is low */
#define	AR_GPIOCR_INT_SELH	0x00010000	/* Interrupt if pin is high */

#define	AR_SREV_CRETE		4		/* Crete 1st version */
#define	AR_SREV_CRETE_MS	5		/* Crete FCS version */
#define	AR_SREV_CRETE_23	8		/* Crete version 2.3 */

#define	AR_EP_STA_RDERR		0x00000001	/* read error */
#define	AR_EP_STA_RDCMPLT	0x00000002	/* read complete */
#define	AR_EP_STA_WRERR		0x00000004	/* write error */
#define	AR_EP_STA_WRCMPLT	0x00000008	/* write complete */
#define	AR_EP_STA_BITS \
	"\20\1RDERR\2RDCMPLT\3WRERR\4WRCMPLT"

#define	AR_STA_ID1_AP		0x00010000	/* Access Point Operation */
#define	AR_STA_ID1_ADHOC	0x00020000	/* ad hoc Operation */
#define	AR_STA_ID1_PWR_SV	0x00040000	/* power save report enable */
#define	AR_STA_ID1_NO_KEYSRCH	0x00080000	/* key table search disable */
#define	AR_STA_ID1_NO_PSPOLL	0x00100000	/* auto PS-POLL disable */
#define	AR_STA_ID1_PCF		0x00200000	/* PCF observation enable */
#define	AR_STA_ID1_DESC_ANTENNA 0x00400000	/* use antenna in TX desc */
#define	AR_STA_ID1_DEFAULT_ANTENNA 0x00800000	/* toggle default antenna */
#define	AR_STA_ID1_ACKCTS_6MB	0x01000000	/* use 6Mbps for ACK/CTS */
#define	AR_STA_ID1_BITS \
	"\20\20AP\21ADHOC\22PWR_SV\23NO_KEYSRCH\24NO_PSPOLL\25PCF"\
	"\26DESC_ANTENNA\27DEFAULT_ANTENNA\30ACKCTS_6MB"

#define	AR_BSS_ID1_AID		0xffff0000	/* association ID */
#define	AR_BSS_ID1_AID_S	16

#define	AR_TIME_OUT_ACK		0x00001fff	/* ACK timeout */
#define	AR_TIME_OUT_ACK_S	0
#define	AR_TIME_OUT_CTS		0x1fff0000	/* CTS timeout */
#define	AR_TIME_OUT_CTS_S	16

#define	AR_RSSI_THR_BM_THR	0x00000700	/* missed beacon threshold */
#define	AR_RSSI_THR_BM_THR_S	8

#define	AR_RETRY_LMT_SH_RETRY	0x0000000f	/* short frame retry limit */
#define	AR_RETRY_LMT_SH_RETRY_S	0
#define	AR_RETRY_LMT_LG_RETRY	0x000000f0	/* long frame retry limit */
#define	AR_RETRY_LMT_LG_RETRY_S	4
#define	AR_RETRY_LMT_SSH_RETRY	0x00003f00	/* short station retry limit */
#define	AR_RETRY_LMT_SSH_RETRY_S	8
#define	AR_RETRY_LMT_SLG_RETRY	0x000fc000	/* long station retry limit */
#define	AR_RETRY_LMT_SLG_RETRY_S	14
#define	AR_RETRY_LMT_CW_MIN	0x3ff00000	/* minimum contention window */
#define	AR_RETRY_LMT_CW_MIN_S		20

#define	AR_USEC_1		0x0000007f	/* number of clk in 1us */
#define	AR_USEC_1_S		0
#define	AR_USEC_32		0x00003f80	/* number of 32MHz clk in 1us */
#define	AR_USEC_32_S		7
#define	AR_USEC_TX_LATENCY	0x000fc000	/* transmit latency in us */
#define	AR_USEC_TX_LATENCY_S	14
#define	AR_USEC_RX_LATENCY	0x03f00000	/* receive latency in us */
#define	AR_USEC_RX_LATENCY_S	20

#define	AR_BEACON_PERIOD	0x0000ffff	/* beacon period in TU/ms */
#define	AR_BEACON_PERIOD_S	0
#define	AR_BEACON_TIM 		0x007f0000	/* byte offset */
#define	AR_BEACON_TIM_S	16
#define	AR_BEACON_EN		0x00800000	/* beacon transmission enable */
#define	AR_BEACON_RESET_TSF 	0x01000000	/* TSF reset oneshot */
#define	AR_BEACON_BITS	"\20\27ENABLE\30RESET_TSF"

#define	AR_IFS0_SIFS		0x000007ff	/* SIFS in core clock cycles */
#define	AR_IFS0_SIFS_S		0
#define	AR_IFS0_DIFS		0x007ff800	/* DIFS in core clock cycles */
#define	AR_IFS0_DIFS_S		11

#define	AR_IFS1_PIFS		0x00000fff	/* Programmable IFS */
#define	AR_IFS1_PIFS_S		0
#define	AR_IFS1_EIFS		0x03fff000	/* EIFS in core clock cycles */
#define	AR_IFS1_EIFS_S		12
#define	AR_IFS1_CS_EN		0x04000000	/* carrier sense enable */

#define	AR_RX_FILTER_UNICAST	0x00000001	/* unicast frame enable */
#define	AR_RX_FILTER_MULTICAST	0x00000002	/* multicast frame enable */
#define	AR_RX_FILTER_BROADCAST	0x00000004	/* broadcast frame enable */
#define	AR_RX_FILTER_CONTROL	0x00000008	/* control frame enable */
#define	AR_RX_FILTER_BEACON	0x00000010	/* beacon frame enable */
#define	AR_RX_FILTER_PROMISCUOUS 0x00000020	/* promiscuous receive enable */
#define	AR_RX_FILTER_BITS \
	"\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC"

#define	AR_DIAG_SW_DIS_WEP_ACK	0x00000001	/* disable ACK if no key found*/
#define	AR_DIAG_SW_DIS_ACK	0x00000002	/* disable ACK generation */
#define	AR_DIAG_SW_DIS_CTS	0x00000004	/* disable CTS generation */
#define	AR_DIAG_SW_DIS_ENC	0x00000008	/* encryption disable */
#define	AR_DIAG_SW_DIS_DEC	0x00000010	/* decryption disable */
#define	AR_DIAG_SW_DIS_TX	0x00000020	/* TX disable */
#define	AR_DIAG_SW_DIS_RX	0x00000040	/* RX disable */
#define	AR_DIAG_SW_LOOP_BACK	0x00000080	/* TX data loopback enable */
#define	AR_DIAG_SW_CORR_FCS	0x00000100	/* corrupt FCS enable */
#define	AR_DIAG_SW_CHAN_INFO	0x00000200	/* channel information enable */
#define	AR_DIAG_SW_EN_SCRAM_SEED 0x00000400	/* use fixed scrambler seed */
#define	AR_DIAG_SW_SCVRAM_SEED	0x0003f800	/* fixed scrambler seed */
#define	AR_DIAG_SW_DIS_SEQ_INC	0x00040000	/* seq increment disable */
#define	AR_DIAG_SW_FRAME_NV0	0x00080000	/* accept frame vers != 0 */
#define	AR_DIAG_SW_BITS \
	"\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\
	"\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\
	"\22DIS_SEQ_INC\24FRAME_NV0"

#define	AR_RETRY_CNT_SSH	0x0000003f	/* current short retry count */
#define	AR_RETRY_CNT_SLG	0x00000fc0	/* current long retry count */

#define	AR_BACKOFF_CW		0x000003ff	/* current contention window */
#define	AR_BACKOFF_CNT		0x03ff0000	/* backoff count */

#define	AR_KEYTABLE_KEY0(n)	(AR_KEYTABLE(n) + 0)	/* key bit 0-31 */
#define	AR_KEYTABLE_KEY1(n)	(AR_KEYTABLE(n) + 4)	/* key bit 32-47 */
#define	AR_KEYTABLE_KEY2(n)	(AR_KEYTABLE(n) + 8)	/* key bit 48-79 */
#define	AR_KEYTABLE_KEY3(n)	(AR_KEYTABLE(n) + 12)	/* key bit 80-95 */
#define	AR_KEYTABLE_KEY4(n)	(AR_KEYTABLE(n) + 16)	/* key bit 96-127 */
#define	AR_KEYTABLE_TYPE(n)	(AR_KEYTABLE(n) + 20)	/* key type */
#define	AR_KEYTABLE_TYPE_40	0x00000000	/* 40 bit key */
#define	AR_KEYTABLE_TYPE_104	0x00000001	/* 104 bit key */
#define	AR_KEYTABLE_TYPE_128	0x00000003	/* 128 bit key */
#define	AR_KEYTABLE_MAC0(n)	(AR_KEYTABLE(n) + 24)	/* MAC address 1-32 */
#define	AR_KEYTABLE_MAC1(n)	(AR_KEYTABLE(n) + 28)	/* MAC address 33-47 */
#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */

#endif /* _DEV_ATH_AR5210REG_H */