ar5210reg.h

Atheros wifi driver source code

/*
 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2005 Atheros Communications, Inc.
 * All rights reserved.
 *
 * $Id: ar5210reg.h,v 1.1.1.1 2006/09/12 03:45:22 steven Exp $
 */
#ifndef _DEV_ATH_AR5210REG_H
#define _DEV_ATH_AR5210REG_H

/*
 * Register defintions for the Atheros AR5210/5110 MAC/Basedband
 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
 */

#ifndef PCI_VENDOR_ATHEROS
#define	PCI_VENDOR_ATHEROS		0x168c
#endif
#define	PCI_PRODUCT_ATHEROS_AR5210	0x0007
#define	PCI_PRODUCT_ATHEROS_AR5210_OLD	0x0004

/* DMA Registers */
#define	AR_TXDP0	0x0000		/* TX queue pointer 0 register */
#define	AR_TXDP1	0x0004		/* TX queue pointer 1 register */
#define	AR_CR		0x0008		/* Command register */
#define	AR_RXDP		0x000c		/* RX queue descriptor ptr register */
#define	AR_CFG		0x0014		/* Configuration and status register */
#define	AR_ISR		0x001c		/* Interrupt status register */
#define	AR_IMR		0x0020		/* Interrupt mask register */
#define	AR_IER		0x0024		/* Interrupt global enable register */
#define	AR_BCR		0x0028		/* Beacon control register */
#define	AR_BSR		0x002c		/* Beacon status register */
#define	AR_TXCFG	0x0030		/* TX configuration register */
#define	AR_RXCFG	0x0034		/* RX configuration register */
#define	AR_MIBC		0x0040		/* MIB control register */
#define	AR_TOPS		0x0044		/* Timeout prescale register */
#define	AR_RXNOFRM	0x0048		/* RX no frame timeout register */
#define	AR_TXNOFRM	0x004c		/* TX no frame timeout register */
#define	AR_RPGTO	0x0050		/* RX frame gap timeout register */
#define	AR_RFCNT	0x0054		/* RX frame count limit register */
#define	AR_MISC		0x0058		/* Misc control and status register */
#define	AR_RC		0x4000		/* Reset control */
#define	AR_SCR		0x4004		/* Sleep control */
#define	AR_INTPEND	0x4008		/* Interrupt pending */
#define	AR_SFR		0x400c		/* Force sleep */
#define	AR_PCICFG	0x4010		/* PCI configuration */
#define	AR_GPIOCR	0x4014		/* GPIO configuration */
#define	AR_GPIODO	0x4018		/* GPIO data output */
#define	AR_GPIODI	0x401c		/* GPIO data input */
#define	AR_SREV		0x4020		/* Silicon revision */
/* EEPROM Access Registers */
#define	AR_EP_AIR_BASE	0x6000		/* EEPROM access initiation regs base */
#define	AR_EP_AIR(n)	(AR_EP_AIR_BASE + (n)*4)
#define	AR_EP_RDATA	0x6800		/* EEPROM read data register */
#define	AR_EP_STA	0x6c00		/* EEPROM access status register */
/* PCU Registers */
#define	AR_STA_ID0	0x8000		/* Lower 32bits of MAC address */
#define	AR_STA_ID1	0x8004		/* Upper 16bits of MAC address */
#define	AR_BSS_ID0	0x8008		/* Lower 32bits of BSSID */
#define	AR_BSS_ID1	0x800c		/* Upper 16bits of BSSID */
#define	AR_SLOT_TIME	0x8010		/* Length of a back-off */
#define	AR_TIME_OUT	0x8014		/* Timeout to wait for ACK and CTS */
#define	AR_RSSI_THR	0x8018		/* Beacon RSSI warning threshold */
#define	AR_RETRY_LMT	0x801c		/* Short and long frame retry limit */
#define	AR_USEC		0x8020		/* Transmit latency */
#define	AR_BEACON	0x8024		/* Beacon control */
#define	AR_CFP_PERIOD	0x8028		/* CFP period */
#define	AR_TIMER0	0x802c		/* Next beacon time */
#define	AR_TIMER1	0x8030		/* Next DMA beacon alert time */
#define	AR_TIMER2	0x8034		/* Next software beacon alert time */
#define	AR_TIMER3	0x8038		/* Next ATIM window time */
#define	AR_IFS0		0x8040		/* Protocol timers */
#define	AR_IFS1		0x8044		/* Protocol time and control */
#define	AR_CFP_DUR	0x8048		/* Maximum CFP duration */
#define	AR_RX_FILTER	0x804c		/* Receive filter */
#define	AR_MCAST_FIL0	0x8050		/* Lower 32bits of mcast filter mask */
#define	AR_MCAST_FIL1	0x8054		/* Upper 16bits of mcast filter mask */
#define	AR_TX_MASK0	0x8058		/* Lower 32bits of TX mask */
#define	AR_TX_MASK1	0x805c		/* Upper 16bits of TX mask */
#define	AR_CLR_TMASK	0x8060		/* Clear TX mask */
#define	AR_TRIG_LEV	0x8064		/* Minimum FIFO fill level before TX */
#define	AR_DIAG_SW	0x8068		/* PCU control */
#define	AR_TSF_L32	0x806c		/* Lower 32bits of local clock */
#define	AR_TSF_U32	0x8070		/* Upper 32bits of local clock */
#define	AR_LAST_TSTP	0x8080		/* Lower 32bits of last beacon tstamp */
#define	AR_RETRY_CNT	0x8084		/* Current short or long retry cnt */
#define	AR_BACKOFF	0x8088		/* Back-off status */
#define	AR_NAV		0x808c		/* Current NAV value */
#define	AR_RTS_OK	0x8090		/* RTS success counter */
#define	AR_RTS_FAIL	0x8094		/* RTS failure counter */
#define	AR_ACK_FAIL	0x8098		/* ACK failure counter */
#define	AR_FCS_FAIL	0x809c		/* FCS failure counter */
#define	AR_BEACON_CNT	0x80a0		/* Valid beacon counter */
#define	AR_KEYTABLE_0	0x9000		/* Encryption key table */
#define	AR_KEYTABLE(n)	(AR_KEYTABLE_0 + ((n)*32))

#define	AR_CR_TXE0		0x00000001	/* TX queue 0 enable */
#define	AR_CR_TXE1		0x00000002	/* TX queue 1 enable */
#define	AR_CR_RXE		0x00000004	/* RX enable */
#define	AR_CR_TXD0		0x00000008	/* TX queue 0 disable */
#define	AR_CR_TXD1		0x00000010	/* TX queue 1 disable */
#define	AR_CR_RXD		0x00000020	/* RX disable */
#define	AR_CR_SWI		0x00000040	/* software interrupt */
#define	AR_CR_BITS \
	"\20\1TXE0\2TXE1\3RXE\4TXD0\5TXD1\6RXD\7SWI"

#define	AR_CFG_SWTD		0x00000001	/* BE for TX desc */
#define	AR_CFG_SWTB		0x00000002	/* BE for TX data */
#define	AR_CFG_SWRD		0x00000004	/* BE for RX desc */
#define	AR_CFG_SWRB		0x00000008	/* BE for RX data */
#define	AR_CFG_SWRG		0x00000010	/* BE for registers */
#define	AR_CFG_EEBS		0x00000200	/* EEPROM busy */
#define	AR_CFG_TXCNT		0x00007800	/* number of TX desc in Q */
#define	AR_CFG_TXCNT_S		11
#define	AR_CFG_TXFSTAT		0x00008000	/* TX DMA status */
#define	AR_CFG_TXFSTRT		0x00010000	/* re-enable TX DMA */
#define	AR_CFG_BITS \
	"\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\14EEBS\17TXFSTAT\20TXFSTRT"

#define	AR_ISR_RXOK_INT		0x00000001	/* RX frame OK */
#define	AR_ISR_RXDESC_INT	0x00000002	/* RX intr request */
#define	AR_ISR_RXERR_INT	0x00000004	/* RX error */
#define	AR_ISR_RXNOFRM_INT	0x00000008	/* no frame received */
#define	AR_ISR_RXEOL_INT	0x00000010	/* RX desc empty */
#define	AR_ISR_RXORN_INT	0x00000020	/* RX fifo overrun */
#define	AR_ISR_TXOK_INT		0x00000040	/* TX frame OK */
#define	AR_ISR_TXDESC_INT	0x00000080	/* TX intr request */
#define	AR_ISR_TXERR_INT	0x00000100	/* TX error */
#define	AR_ISR_TXNOFRM_INT	0x00000200	/* no frame transmitted */
#define	AR_ISR_TXEOL_INT	0x00000400	/* TX desc empty */
#define	AR_ISR_TXURN_INT	0x00000800	/* TX fifo underrun */
#define	AR_ISR_MIB_INT		0x00001000	/* MIB interrupt */
#define	AR_ISR_SWI_INT		0x00002000	/* software interrupt */
#define	AR_ISR_RXPHY_INT	0x00004000	/* PHY RX error */
#define	AR_ISR_RXKCM_INT	0x00008000	/* Key cache miss */
#define	AR_ISR_SWBA_INT		0x00010000	/* software beacon alert */
#define	AR_ISR_BRSSI_INT	0x00020000	/* beacon threshold */
#define	AR_ISR_BMISS_INT	0x00040000	/* beacon missed */
#define	AR_ISR_MCABT_INT	0x00100000	/* master cycle abort */
#define	AR_ISR_SSERR_INT	0x00200000	/* SERR on PCI */
#define	AR_ISR_DPERR_INT	0x00400000	/* Parity error on PCI */
#define	AR_ISR_GPIO_INT		0x01000000	/* GPIO interrupt */
#define	AR_ISR_BITS \
	"\20\1RXOK\2RXDESC\3RXERR\4RXNOFM\5RXEOL\6RXORN\7TXOK\10TXDESC"\
	"\11TXERR\12TXNOFRM\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"\
	"\21SWBA\22BRSSI\23BMISS\24MCABT\25SSERR\26DPERR\27GPIO"

#define	AR_IMR_RXOK_INT		0x00000001	/* RX frame OK */
#define	AR_IMR_RXDESC_INT	0x00000002	/* RX intr request */
#define	AR_IMR_RXERR_INT	0x00000004	/* RX error */
#define	AR_IMR_RXNOFRM_INT	0x00000008	/* no frame received */
#define	AR_IMR_RXEOL_INT	0x00000010	/* RX desc empty */
#define	AR_IMR_RXORN_INT	0x00000020	/* RX fifo overrun */
#define	AR_IMR_TXOK_INT		0x00000040	/* TX frame OK */
#define	AR_IMR_TXDESC_INT	0x00000080	/* TX intr request */
#define	AR_IMR_TXERR_INT	0x00000100	/* TX error */
#define	AR_IMR_TXNOFRM_INT	0x00000200	/* no frame transmitted */
#define	AR_IMR_TXEOL_INT	0x00000400	/* TX desc empty */
#define	AR_IMR_TXURN_INT	0x00000800	/* TX fifo underrun */
#define	AR_IMR_MIB_INT		0x00001000	/* MIB interrupt */
#define	AR_IMR_SWI_INT		0x00002000	/* software interrupt */
#define	AR_IMR_RXPHY_INT	0x00004000	/* PHY RX error */
#define	AR_IMR_RXKCM_INT	0x00008000	/* Key cache miss */
#define	AR_IMR_SWBA_INT		0x00010000	/* software beacon alert */
#define	AR_IMR_BRSSI_INT	0x00020000	/* beacon threshold */
#define	AR_IMR_BMISS_INT	0x00040000	/* beacon missed */
#define	AR_IMR_MCABT_INT	0x00100000	/* master cycle abort */
#define	AR_IMR_SSERR_INT	0x00200000	/* SERR on PCI */
#define	AR_IMR_DPERR_INT	0x00400000	/* Parity error on PCI */
#define	AR_IMR_GPIO_INT		0x01000000	/* GPIO interrupt */
#define	AR_IMR_BITS	AR_ISR_BITS

#define	AR_IER_DISABLE		0x00000000	/* pseudo-flag */
#define	AR_IER_ENABLE		0x00000001	/* global interrupt enable */
#define	AR_IER_BITS	"\20\1ENABLE"

#define	AR_BCR_BCMD		0x00000001	/* ad hoc beacon mode */
#define	AR_BCR_BDMAE		0x00000002	/* beacon DMA enable */
#define	AR_BCR_TQ1FV		0x00000004	/* use TXQ1 for non-beacon */
#define	AR_BCR_TQ1V		0x00000008	/* TXQ1 valid for beacon */
#define	AR_BCR_BCGET		0x00000010	/* force a beacon fetch */
#define	AR_BCR_BITS	"\20\1BCMD\2BDMAE\3TQ1FV\4TQ1V\5BCGET"

#define	AR_BSR_BDLYSW		0x00000001	/* software beacon delay */
#define	AR_BSR_BDLYDMA		0x00000002	/* DMA beacon delay */
#define	AR_BSR_TXQ1F		0x00000004	/* TXQ1 fetch */
#define	AR_BSR_ATIMDLY		0x00000008	/* ATIM delay */
#define	AR_BSR_SNPBCMD		0x00000100	/* snapshot of BCMD */
#define	AR_BSR_SNPBDMAE		0x00000200	/* snapshot of BDMAE */
#define	AR_BSR_SNPTQ1FV		0x00000400	/* snapshot of TQ1FV */
#define	AR_BSR_SNPTQ1V		0x00000800	/* snapshot of TQ1V */
#define	AR_BSR_SNAPPEDBCRVALID	0x00001000	/* snapshot of BCR are valid */
#define	AR_BSR_SWBA_CNT		0x00ff0000	/* software beacon alert cnt */
#define	AR_BSR_BITS \
	"\20\1BDLYSW\2BDLYDMA\3TXQ1F\4ATIMDLY\11SNPBCMD\12SNPBDMAE"\
	"\13SNPTQ1FV\14SNPTQ1V\15SNAPPEDBCRVALID"