ar5210_xmit.c

Atheros wifi driver source code

 * Returns TRUE if the trigger level was updated
 */
HAL_BOOL
ar5210UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
{
	u_int32_t curTrigLevel;
	HAL_INT ints = ar5210GetInterrupts(ah);

	/*
	 * Disable chip interrupts. This is because halUpdateTxTrigLevel
	 * is called from both ISR and non-ISR contexts.
	 */
	(void) ar5210SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
	curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);
	if (bIncTrigLevel){
		/* increase the trigger level */
		curTrigLevel = curTrigLevel +
			((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
	} else {
		/* decrease the trigger level if not already at the minimum */
		if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
			/* decrease the trigger level */
			curTrigLevel--;
		} else {
			/* no update to the trigger level */
			/* re-enable chip interrupts */
			ar5210SetInterrupts(ah, ints);
			return AH_FALSE;
		}
	}
	/* Update the trigger level */
	OS_REG_WRITE(ah, AR_TRIG_LEV, curTrigLevel);
	/* re-enable chip interrupts */
	ar5210SetInterrupts(ah, ints);
	return AH_TRUE;
}

/*
 * Set Transmit Enable bits for the specified queues.
 */
HAL_BOOL
ar5210StartTxDma(struct ath_hal *ah, u_int q)
{
	struct ath_hal_5210 *ahp = AH5210(ah);
	HAL_TX_QUEUE_INFO *qi;

	HALASSERT(q < HAL_NUM_TX_QUEUES);

	HALDEBUGn(ah, 2, "%s: queue %u\n", __func__, q);
	qi = &ahp->ah_txq[q];
	switch (qi->tqi_type) {
	case HAL_TX_QUEUE_DATA:
		OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
		break;
	case HAL_TX_QUEUE_CAB:
		OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1);	/* enable altq xmit */
		OS_REG_WRITE(ah, AR_BCR,
			AR_BCR_TQ1V | AR_BCR_BDMAE | AR_BCR_TQ1FV);
		break;
	case HAL_TX_QUEUE_BEACON:
		/* XXX add CR_BCR_BCMD if IBSS mode */
		OS_REG_WRITE(ah, AR_BCR, AR_BCR_TQ1V | AR_BCR_BDMAE);
		break;
	case HAL_TX_QUEUE_INACTIVE:
		HALDEBUG(ah, "%s: inactive queue %u\n", __func__, q);
		/* fal thru... */
	default:
		return AH_FALSE;
	}
	return AH_TRUE;
}

u_int32_t
ar5210NumTxPending(struct ath_hal *ah, u_int q)
{
	struct ath_hal_5210 *ahp = AH5210(ah);
	HAL_TX_QUEUE_INFO *qi;
	u_int32_t v;

	HALASSERT(q < HAL_NUM_TX_QUEUES);

	HALDEBUG(ah, "%s: queue %u\n", __func__, q);
	qi = &ahp->ah_txq[q];
	switch (qi->tqi_type) {
	case HAL_TX_QUEUE_DATA:
		v = OS_REG_READ(ah, AR_CFG);
		return MS(v, AR_CFG_TXCNT);
	case HAL_TX_QUEUE_INACTIVE:
		HALDEBUG(ah, "%s: inactive queue %u\n", __func__, q);
		/* fall thru... */
	default:
		break;
	}
	return 0;
}

/*
 * Stop transmit on the specified queue
 */
HAL_BOOL
ar5210StopTxDma(struct ath_hal *ah, u_int q)
{
	struct ath_hal_5210 *ahp = AH5210(ah);
	HAL_TX_QUEUE_INFO *qi;

	HALASSERT(q < HAL_NUM_TX_QUEUES);

	HALDEBUGn(ah, 2, "%s: queue %u\n", __func__, q);
	qi = &ahp->ah_txq[q];
	switch (qi->tqi_type) {
	case HAL_TX_QUEUE_DATA: {
		int i;
		OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
		for (i = 0; i < 1000; i++) {
			if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)
				break;
			OS_DELAY(10);
		}
		OS_REG_WRITE(ah, AR_CR, 0);
		return (i < 1000);
	}
	case HAL_TX_QUEUE_BEACON:
		return ath_hal_wait(ah, AR_BSR, AR_BSR_TXQ1F, 0);
	case HAL_TX_QUEUE_INACTIVE:
		HALDEBUG(ah, "%s: inactive queue %u\n", __func__, q);
		/* fall thru... */
	default:
		break;
	}
	return AH_FALSE;
}

HAL_BOOL
ar5210UpdateCTSForBursting(struct ath_hal *ah, struct ath_desc *ds,
	struct ath_desc *prevds,
	struct ath_desc *prevdsWithCTS,
	struct ath_desc *gatingds,	
	u_int32_t txOpLimit /* in us */,
	u_int32_t ctsDuration)
{
	return 1;
}
/*
 * Descriptor Access Functions
 */

#define	VALID_PKT_TYPES \
	((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
	 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
	 (1<<HAL_PKT_TYPE_BEACON))
#define	isValidPktType(_t)	((1<<(_t)) & VALID_PKT_TYPES)
#define	VALID_TX_RATES \
	((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
	 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
	 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
#define	isValidTxRate(_r)	((1<<(_r)) & VALID_TX_RATES)

HAL_BOOL
ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
	u_int pktLen,
	u_int hdrLen,
	HAL_PKT_TYPE type,
	u_int txPower,
	u_int txRate0, u_int txTries0,
	u_int keyIx,
	u_int antMode,
	u_int flags,
	u_int rtsctsRate,
	u_int rtsctsDuration,
        u_int compicvLen,
	u_int compivLen,
	u_int comp)
{
	struct ar5210_desc *ads = AR5210DESC(ds);
	u_int32_t frtype;

	(void) txPower;
	(void) rtsctsDuration;

	HALASSERT(txTries0 != 0);
	HALASSERT(isValidPktType(type));
	HALASSERT(isValidTxRate(txRate0));

	if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
		frtype = AR_Frm_NoDelay;
	else
		frtype = type << 26;
	ads->ds_ctl0 = (pktLen & AR_FrameLen)
		     | (txRate0 << AR_XmitRate_S)
		     | ((hdrLen << AR_HdrLen_S) & AR_HdrLen)
		     | frtype
		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
		     | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
		     | (antMode ? AR_AntModeXmit : 0)
		     ;
	if (keyIx != HAL_TXKEYIX_INVALID) {
		ads->ds_ctl1 = (keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
		ads->ds_ctl0 |= AR_EncryptKeyValid;
	} else
		ads->ds_ctl1 = 0;
	if (flags & HAL_TXDESC_RTSENA) {
		ads->ds_ctl0 |= AR_RTSCTSEnable;
		ads->ds_ctl1 |= rtsctsDuration & AR_RTSDuration;
	}
	return AH_TRUE;
}

HAL_BOOL
ar5210SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
	u_int txRate1, u_int txTries1,
	u_int txRate2, u_int txTries2,
	u_int txRate3, u_int txTries3)
{
	(void) ah; (void) ds;
	(void) txRate1; (void) txTries1;
	(void) txRate2; (void) txTries2;
	(void) txRate3; (void) txTries3;
	return AH_FALSE;
}

void
ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
{
	struct ar5210_desc *ads = AR5210DESC(ds);

	ads->ds_ctl0 |= AR_TxInterReq;
}

HAL_BOOL
ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
	u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
	const struct ath_desc *ds0)
{
	struct ar5210_desc *ads = AR5210DESC(ds);

	HALASSERT((segLen &~ AR_BufLen) == 0);

	if (firstSeg) {
		/*
		 * First descriptor, don't clobber xmit control data
		 * setup by ar5210SetupTxDesc.
		 */
		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
	} else if (lastSeg) {		/* !firstSeg && lastSeg */
		/*
		 * Last descriptor in a multi-descriptor frame,
		 * copy the transmit parameters from the first
		 * frame for processing on completion. 
		 */
		ads->ds_ctl0 = AR5210DESC_CONST(ds0)->ds_ctl0;
		ads->ds_ctl1 = segLen;
	} else {			/* !firstSeg && !lastSeg */
		/*
		 * Intermediate descriptor in a multi-descriptor frame.
		 */
		ads->ds_ctl0 = 0;
		ads->ds_ctl1 = segLen | AR_More;
	}
	ads->ds_status0 = ads->ds_status1 = 0;
	return AH_TRUE;
}

/*
 * Processing of HW TX descriptor.
 */
HAL_STATUS
ar5210ProcTxDesc(struct ath_hal *ah, struct ath_desc *ds)
{
	struct ar5210_desc *ads = AR5210DESC(ds);

	if ((ads->ds_status1 & AR_Done) == 0)
		return HAL_EINPROGRESS;

	/* Update software copies of the HW status */
	ds->ds_txstat->ts_seqnum = ads->ds_status1 & AR_SeqNum;
	ds->ds_txstat->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
	ds->ds_txstat->ts_status = 0;
	if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
		if (ads->ds_status0 & AR_ExcessiveRetries)
			ds->ds_txstat->ts_status |= HAL_TXERR_XRETRY;
		if (ads->ds_status0 & AR_Filtered)
			ds->ds_txstat->ts_status |= HAL_TXERR_FILT;
		if (ads->ds_status0  & AR_FIFOUnderrun)
			ds->ds_txstat->ts_status |= HAL_TXERR_FIFO;
	}
	ds->ds_txstat->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
	ds->ds_txstat->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
	ds->ds_txstat->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
	ds->ds_txstat->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
	ds->ds_txstat->ts_antenna = 0;		/* NB: don't know */

	return HAL_OK;
}

/*
 * Determine which tx queues need interrupt servicing.
 * STUB.
 */
void
ar5210GetTxIntrQueue(struct ath_hal *ah, u_int32_t *txqs)
{
	return;
}
#endif /* AH_SUPPORT_AR5210 */