lisa1.sdf

proteus 的51实验板 .

X0236850C#7,PPROBE,,PIN=00000006:0236850C:00000007,PRIMITIVE=PASSIVE
X0236850C#8,PPROBE,,PIN=00000006:0236850C:00000008,PRIMITIVE=PASSIVE
X0322184C#0,PPROBE,,PIN=0000001B:0322184C:00000000,PRIMITIVE=PASSIVE
X0322184C#1,PPROBE,,PIN=0000001B:0322184C:00000001,PRIMITIVE=PASSIVE
X0322559C#0,PPROBE,,PIN=00000027:0322559C:00000000,PRIMITIVE=PASSIVE
X0322559C#1,PPROBE,,PIN=00000027:0322559C:00000001,PRIMITIVE=PASSIVE
X0322559C#2,PPROBE,,PIN=00000027:0322559C:00000002,PRIMITIVE=PASSIVE
X0322559C#3,PPROBE,,PIN=00000027:0322559C:00000003,PRIMITIVE=PASSIVE
X02369910#0,PPROBE,,PIN=00000008:02369910:00000000,PRIMITIVE=PASSIVE
X02369910#1,PPROBE,,PIN=00000008:02369910:00000001,PRIMITIVE=PASSIVE
X03221150#0,PPROBE,,PIN=00000019:03221150:00000000,PRIMITIVE=PASSIVE
X03221150#1,PPROBE,,PIN=00000019:03221150:00000001,PRIMITIVE=PASSIVE
X03222608#0,PPROBE,,PIN=0000001D:03222608:00000000,PRIMITIVE=PASSIVE
X03222608#1,PPROBE,,PIN=0000001D:03222608:00000001,PRIMITIVE=PASSIVE
X03222608#2,PPROBE,,PIN=0000001D:03222608:00000002,PRIMITIVE=PASSIVE
X03222608#3,PPROBE,,PIN=0000001D:03222608:00000003,PRIMITIVE=PASSIVE
X03222608#6,PPROBE,,PIN=0000001D:03222608:00000006,PRIMITIVE=PASSIVE
X03222608#7,PPROBE,,PIN=0000001D:03222608:00000007,PRIMITIVE=PASSIVE
X03223100#0,PPROBE,,PIN=00000025:03223100:00000000,PRIMITIVE=PASSIVE
X03223100#1,PPROBE,,PIN=00000025:03223100:00000001,PRIMITIVE=PASSIVE
X03223100#2,PPROBE,,PIN=00000025:03223100:00000002,PRIMITIVE=PASSIVE
X03223100#3,PPROBE,,PIN=00000025:03223100:00000003,PRIMITIVE=PASSIVE
X03223100#6,PPROBE,,PIN=00000025:03223100:00000006,PRIMITIVE=PASSIVE
X03223100#7,PPROBE,,PIN=00000025:03223100:00000007,PRIMITIVE=PASSIVE
X03224138#0,PPROBE,,PIN=00000020:03224138:00000000,PRIMITIVE=PASSIVE
X03224138#1,PPROBE,,PIN=00000020:03224138:00000001,PRIMITIVE=PASSIVE

*NETLIST,462  
#00000,2
U1,OP,XTAL2
X0236D03C#0,IP,*

#00001,2
U1,IP,XTAL1
X0236D03C#1,IP,*

#00002,2
U1,OP,ALE
X0236D03C#2,IP,*

#00003,2
U1,IP,$EA$
X0236D03C#3,IP,*

#00004,2
U1,OP,$PSEN$
X0236D03C#4,IP,*

#00005,2
U1,IP,RST
X0236D03C#5,IP,*

#00014,6
U1,IO,P1.0/T2
X0236D03C#14,IP,*
$IOSCILLOSCOPE#0027,IP,C
X0322559C#2,IP,*
U8,IP,CONV
X03222608#7,IP,*

#00015,6
U1,IO,P1.1/T2EX
X0236D03C#15,IP,*
U8,OP,SDO
X03222608#3,IP,*
$IOSCILLOSCOPE#0027,IP,A
X0322559C#0,IP,*

#00016,6
U1,IO,P1.2
X0236D03C#16,IP,*
U8,IP,SCK
X03222608#6,IP,*
$IOSCILLOSCOPE#0027,IP,B
X0322559C#1,IP,*

#00022,2
U1,IO,P3.0/RXD
X0236D03C#22,IP,*

#00023,4
U1,IO,P3.1/TXD
X0236D03C#23,IP,*
$IVIRTUAL TERMINAL#0007,IP,RXD
X023680F8#0,IP,*

#00024,2
U1,IO,P3.2/$INT0$
X0236D03C#24,IP,*

#00025,2
U1,IO,P3.3/$INT1$
X0236D03C#25,IP,*

#00026,2
U1,IO,P3.4/T0
X0236D03C#26,IP,*

#00027,2
U1,IO,P3.7/$RD$
X0236D03C#27,IP,*

#00028,2
U1,IO,P3.6/$WR$
X0236D03C#28,IP,*

#00029,2
U1,IO,P3.5/T1
X0236D03C#29,IP,*

#00036,4
U1,IO,P2.3/A11
X0236D03C#36,IP,*
BUTTON#0006,PS,1
X026B976C#0,IP,*

#00037,4
U1,IO,P2.4/A12
X0236D03C#37,IP,*
BUTTON#0023,PS,1
X03224138#0,IP,*

#00038,2
U1,IO,P2.5/A13
X0236D03C#38,IP,*

#00061,2
$IVIRTUAL TERMINAL#0007,OP,RTS
X023680F8#1,IP,*

#00062,2
$IVIRTUAL TERMINAL#0007,OP,TXD
X023680F8#2,IP,*

#00063,2
$IVIRTUAL TERMINAL#0007,IP,CTS
X023680F8#3,IP,*

#00066,2
R1,PS,2
X02369910#1,IP,*

#00130,4
U8,IP,VCH0
X03222608#0,IP,*
RV2,PS,3
X032263D0#2,IP,*

#00131,4
U8,IP,VCH1
X03222608#1,IP,*
RV1,PS,3
X032251A0#2,IP,*

#00132,2
U8,IP,SDI
X03222608#2,IP,*

#00145,2
$IOSCILLOSCOPE#0027,IP,D
X0322559C#3,IP,*

#U3#00218,1
U3_U1,OP,ACK_IN

#U3#00219,1
U3_U2,IP,$RESET$

#U4#00255,1
U4_I2C,PS,S

#U4#00256,1
U4_I2C,PS,Sr

#U4#00257,1
U4_I2C,PS,P

#U4#00258,1
U4_I2C,OP,ACK_IN

#U4#00259,2
U4_U3,OP,Q
U4_U1,IP,OE

#U4#00260,2
U4_QASSI-IO 0_U1,OP,Q
U4_QASSI-IO 0_U6,IP,D1

#U4#00261,3
U4_QASSI-IO 0_U1,OP,!Q
U4_QASSI-IO 0_U5,IP,D1
U4_QASSI-IO 0_U7,IP,D

#U4#00262,1
U4_QASSI-IO 0_U1,IP,RESET

#U4#00263,1
U4_QASSI-IO 0_U1,IP,SET

#U4#00264,2
U4_QASSI-IO 0_U2,IP,CLK
U4_QASSI-IO 0_U3,OP,Q

#U4#00265,1
U4_QASSI-IO 0_U2,OP,Q

#U4#00266,1
U4_QASSI-IO 0_U2,IP,RESET

#U4#00267,1
U4_QASSI-IO 0_U2,IP,SET

#U4#00268,2
U4_QASSI-IO 0_U5,OP,Q
U4_QASSI-IO 0_U6,IP,D0

#U4#00269,2
U4_QASSI-IO 0_U7,IP,OE
U4_QASSI-IO 0_U6,OP,Q

#U4#00270,2
U4_QASSI-IO 1_U1,OP,Q
U4_QASSI-IO 1_U6,IP,D1

#U4#00271,3
U4_QASSI-IO 1_U1,OP,!Q
U4_QASSI-IO 1_U5,IP,D1
U4_QASSI-IO 1_U7,IP,D

#U4#00272,1
U4_QASSI-IO 1_U1,IP,RESET

#U4#00273,1
U4_QASSI-IO 1_U1,IP,SET

#U4#00274,2
U4_QASSI-IO 1_U2,IP,CLK
U4_QASSI-IO 1_U3,OP,Q

#U4#00275,1
U4_QASSI-IO 1_U2,OP,Q

#U4#00276,1
U4_QASSI-IO 1_U2,IP,RESET

#U4#00277,1
U4_QASSI-IO 1_U2,IP,SET

#U4#00278,2
U4_QASSI-IO 1_U5,OP,Q
U4_QASSI-IO 1_U6,IP,D0

#U4#00279,2
U4_QASSI-IO 1_U7,IP,OE
U4_QASSI-IO 1_U6,OP,Q

#U4#00280,2
U4_QASSI-IO 2_U1,OP,Q
U4_QASSI-IO 2_U6,IP,D1

#U4#00281,3
U4_QASSI-IO 2_U1,OP,!Q
U4_QASSI-IO 2_U5,IP,D1
U4_QASSI-IO 2_U7,IP,D

#U4#00282,1
U4_QASSI-IO 2_U1,IP,RESET

#U4#00283,1
U4_QASSI-IO 2_U1,IP,SET

#U4#00284,2
U4_QASSI-IO 2_U2,IP,CLK
U4_QASSI-IO 2_U3,OP,Q

#U4#00285,1
U4_QASSI-IO 2_U2,OP,Q

#U4#00286,1
U4_QASSI-IO 2_U2,IP,RESET

#U4#00287,1
U4_QASSI-IO 2_U2,IP,SET

#U4#00288,2
U4_QASSI-IO 2_U5,OP,Q
U4_QASSI-IO 2_U6,IP,D0

#U4#00289,2
U4_QASSI-IO 2_U7,IP,OE
U4_QASSI-IO 2_U6,OP,Q

#U4#00290,2
U4_QASSI-IO 3_U1,OP,Q
U4_QASSI-IO 3_U6,IP,D1

#U4#00291,3
U4_QASSI-IO 3_U1,OP,!Q
U4_QASSI-IO 3_U5,IP,D1
U4_QASSI-IO 3_U7,IP,D

#U4#00292,1
U4_QASSI-IO 3_U1,IP,RESET

#U4#00293,1
U4_QASSI-IO 3_U1,IP,SET

#U4#00294,2
U4_QASSI-IO 3_U2,IP,CLK
U4_QASSI-IO 3_U3,OP,Q

#U4#00295,1
U4_QASSI-IO 3_U2,OP,Q

#U4#00296,1
U4_QASSI-IO 3_U2,IP,RESET

#U4#00297,1
U4_QASSI-IO 3_U2,IP,SET

#U4#00298,2
U4_QASSI-IO 3_U5,OP,Q
U4_QASSI-IO 3_U6,IP,D0

#U4#00299,2
U4_QASSI-IO 3_U7,IP,OE
U4_QASSI-IO 3_U6,OP,Q

#U4#00300,2
U4_QASSI-IO 4_U1,OP,Q
U4_QASSI-IO 4_U6,IP,D1

#U4#00301,3
U4_QASSI-IO 4_U1,OP,!Q
U4_QASSI-IO 4_U5,IP,D1
U4_QASSI-IO 4_U7,IP,D

#U4#00302,1
U4_QASSI-IO 4_U1,IP,RESET

#U4#00303,1
U4_QASSI-IO 4_U1,IP,SET

#U4#00304,2
U4_QASSI-IO 4_U2,IP,CLK
U4_QASSI-IO 4_U3,OP,Q

#U4#00305,1
U4_QASSI-IO 4_U2,OP,Q

#U4#00306,1
U4_QASSI-IO 4_U2,IP,RESET

#U4#00307,1
U4_QASSI-IO 4_U2,IP,SET

#U4#00308,2
U4_QASSI-IO 4_U5,OP,Q
U4_QASSI-IO 4_U6,IP,D0

#U4#00309,2
U4_QASSI-IO 4_U7,IP,OE
U4_QASSI-IO 4_U6,OP,Q

#U4#00310,2
U4_QASSI-IO 5_U1,OP,Q
U4_QASSI-IO 5_U6,IP,D1

#U4#00311,3
U4_QASSI-IO 5_U1,OP,!Q
U4_QASSI-IO 5_U5,IP,D1
U4_QASSI-IO 5_U7,IP,D

#U4#00312,1
U4_QASSI-IO 5_U1,IP,RESET

#U4#00313,1
U4_QASSI-IO 5_U1,IP,SET

#U4#00314,2
U4_QASSI-IO 5_U2,IP,CLK
U4_QASSI-IO 5_U3,OP,Q

#U4#00315,1
U4_QASSI-IO 5_U2,OP,Q

#U4#00316,1
U4_QASSI-IO 5_U2,IP,RESET

#U4#00317,1
U4_QASSI-IO 5_U2,IP,SET

#U4#00318,2
U4_QASSI-IO 5_U5,OP,Q
U4_QASSI-IO 5_U6,IP,D0

#U4#00319,2
U4_QASSI-IO 5_U7,IP,OE
U4_QASSI-IO 5_U6,OP,Q

#U4#00320,2
U4_QASSI-IO 6_U1,OP,Q
U4_QASSI-IO 6_U6,IP,D1

#U4#00321,3
U4_QASSI-IO 6_U1,OP,!Q
U4_QASSI-IO 6_U5,IP,D1
U4_QASSI-IO 6_U7,IP,D

#U4#00322,1
U4_QASSI-IO 6_U1,IP,RESET

#U4#00323,1
U4_QASSI-IO 6_U1,IP,SET

#U4#00324,2
U4_QASSI-IO 6_U2,IP,CLK
U4_QASSI-IO 6_U3,OP,Q

#U4#00325,1
U4_QASSI-IO 6_U2,OP,Q

#U4#00326,1
U4_QASSI-IO 6_U2,IP,RESET

#U4#00327,1
U4_QASSI-IO 6_U2,IP,SET

#U4#00328,2
U4_QASSI-IO 6_U5,OP,Q
U4_QASSI-IO 6_U6,IP,D0

#U4#00329,2
U4_QASSI-IO 6_U7,IP,OE
U4_QASSI-IO 6_U6,OP,Q

#U4#00330,2
U4_QASSI-IO 7_U1,OP,Q
U4_QASSI-IO 7_U6,IP,D1

#U4#00331,3
U4_QASSI-IO 7_U1,OP,!Q
U4_QASSI-IO 7_U5,IP,D1
U4_QASSI-IO 7_U7,IP,D

#U4#00332,1
U4_QASSI-IO 7_U1,IP,RESET

#U4#00333,1
U4_QASSI-IO 7_U1,IP,SET

#U4#00334,2
U4_QASSI-IO 7_U2,IP,CLK
U4_QASSI-IO 7_U3,OP,Q

#U4#00335,1
U4_QASSI-IO 7_U2,OP,Q

#U4#00336,1
U4_QASSI-IO 7_U2,IP,RESET

#U4#00337,1
U4_QASSI-IO 7_U2,IP,SET

#U4#00338,2
U4_QASSI-IO 7_U5,OP,Q
U4_QASSI-IO 7_U6,IP,D0

#U4#00339,2
U4_QASSI-IO 7_U7,IP,OE
U4_QASSI-IO 7_U6,OP,Q

#U4#00340,2
U4_QASSI-IO 0_U4,OP,Q
U4_U3,IP,D0

#U4#00341,2
U4_QASSI-IO 1_U4,OP,Q
U4_U3,IP,D1

#U4#00342,2
U4_QASSI-IO 2_U4,OP,Q
U4_U3,IP,D2

#U4#00343,2
U4_QASSI-IO 3_U4,OP,Q
U4_U3,IP,D3

#U4#00344,2
U4_QASSI-IO 4_U4,OP,Q
U4_U3,IP,D4

#U4#00345,2
U4_QASSI-IO 5_U4,OP,Q
U4_U3,IP,D5

#U4#00346,2
U4_QASSI-IO 6_U4,OP,Q
U4_U3,IP,D6

#U4#00347,9
U4_QASSI-IO 7_U3,IP,D1
U4_QASSI-IO 6_U3,IP,D1
U4_QASSI-IO 5_U3,IP,D1
U4_QASSI-IO 4_U3,IP,D1
U4_QASSI-IO 3_U3,IP,D1
U4_QASSI-IO 2_U3,IP,D1
U4_QASSI-IO 1_U3,IP,D1
U4_QASSI-IO 0_U3,IP,D1
U4_I2C,OP,DOUT_STROBE

#U4#00348,25
U4_QASSI-IO 7_U1,IP,CLK
U4_QASSI-IO 7_U3,IP,D0
U4_QASSI-IO 7_U5,IP,D0
U4_QASSI-IO 6_U1,IP,CLK
U4_QASSI-IO 6_U3,IP,D0
U4_QASSI-IO 6_U5,IP,D0
U4_QASSI-IO 5_U1,IP,CLK
U4_QASSI-IO 5_U3,IP,D0
U4_QASSI-IO 5_U5,IP,D0
U4_QASSI-IO 4_U1,IP,CLK
U4_QASSI-IO 4_U3,IP,D0
U4_QASSI-IO 4_U5,IP,D0
U4_QASSI-IO 3_U1,IP,CLK
U4_QASSI-IO 3_U3,IP,D0
U4_QASSI-IO 3_U5,IP,D0
U4_QASSI-IO 2_U1,IP,CLK
U4_QASSI-IO 2_U3,IP,D0
U4_QASSI-IO 2_U5,IP,D0
U4_QASSI-IO 1_U1,IP,CLK
U4_QASSI-IO 1_U3,IP,D0
U4_QASSI-IO 1_U5,IP,D0
U4_QASSI-IO 0_U1,IP,CLK
U4_QASSI-IO 0_U3,IP,D0
U4_QASSI-IO 0_U5,IP,D0
U4_I2C,OP,DIN_STROBE

#U4#00349,2
U4_QASSI-IO 7_U4,OP,Q
U4_U3,IP,D7

#U5#00386,3
U5_IP1,PS,-
U5_S1,PS,+
U5_S1,PS,P

#U5#00387,3
U5_IP2,PS,-
U5_S2,PS,+
U5_S2,PS,P

#U5#00388,3
U5_IP3,PS,-
U5_S3,PS,+
U5_S3,PS,P

#U5#00389,3
U5_IP4,PS,-