m64.lst

avr的视频采集

    03E3 1E35      ADC	R3,R21
    03E4 1E46      ADC	R4,R22
    03E5 1E57      ADC	R5,R23
    03E6 9220009C  STS	0x9C,R2
(0199) 			if (huanhang)
    03E8 20AA      TST	R10
    03E9 F079      BEQ	0x03F9
(0200) 			 {
(0201) 			  while(!(UCSR1A&(1<<UDRE1)));
    03EA 9020009B  LDS	R2,0x9B
    03EC FE25      SBRS	R2,5
    03ED CFFC      RJMP	0x03EA
(0202) 		      UDR1=0x0d;
    03EE E08D      LDI	R24,0xD
    03EF 9380009C  STS	0x9C,R24
(0203) 			  while(!(UCSR1A&(1<<UDRE1)));
    03F1 9020009B  LDS	R2,0x9B
    03F3 FE25      SBRS	R2,5
    03F4 CFFC      RJMP	0x03F1
(0204) 		      UDR1=0x0a;
    03F5 E08A      LDI	R24,0xA
    03F6 9380009C  STS	0x9C,R24
(0205) 			 }
    03F8 C00E      RJMP	0x0407
(0206) 			 else
(0207) 			 {
(0208) 			  while(!(UCSR1A&(1<<UDRE1)));
    03F9 9020009B  LDS	R2,0x9B
    03FB FE25      SBRS	R2,5
    03FC CFFC      RJMP	0x03F9
(0209) 		      UDR1=0x20;
    03FD E280      LDI	R24,0x20
    03FE 9380009C  STS	0x9C,R24
(0210) 			  while(!(UCSR1A&(1<<UDRE1)));
    0400 9020009B  LDS	R2,0x9B
    0402 FE25      SBRS	R2,5
    0403 CFFC      RJMP	0x0400
(0211) 		      UDR1=0x20;
    0404 E280      LDI	R24,0x20
    0405 9380009C  STS	0x9C,R24
(0212) 			 } 
    0407 9624      ADIW	R28,4
    0408 940E06B3  CALL	pop_gset3
    040A 9624      ADIW	R28,4
    040B 9508      RET
_int0_isr:
    040C 922A      ST	R2,-Y
    040D 923A      ST	R3,-Y
    040E 938A      ST	R24,-Y
    040F B62F      IN	R2,0x3F
    0410 922A      ST	R2,-Y
(0213) }
(0214) 
(0215) unsigned char shuliang=0;
(0216) unsigned char xuanze=0;
(0217) #pragma interrupt_handler int0_isr:2
(0218) void int0_isr(void)
(0219) {
(0220)  //external interupt on INT0
(0221)  
(0222) x_adc=0;y_adc=0;
    0411 2422      CLR	R2
    0412 9220012E  STS	x_adc,R2
    0414 9220012D  STS	y_adc,R2
(0223) chang=1;
    0416 E081      LDI	R24,1
    0417 93800128  STS	chang,R24
(0224)  shuliang=ms;
    0419 90200104  LDS	R2,ms
    041B 90300105  LDS	R3,ms+1
    041D 9220012B  STS	shuliang,R2
(0225)  ms=0;
    041F 2422      CLR	R2
    0420 2433      CLR	R3
    0421 92300105  STS	ms+1,R3
    0423 92200104  STS	ms,R2
    0425 9029      LD	R2,Y+
    0426 BE2F      OUT	0x3F,R2
    0427 9189      LD	R24,Y+
    0428 9039      LD	R3,Y+
    0429 9029      LD	R2,Y+
    042A 9518      RETI
_int1_isr:
    042B 922A      ST	R2,-Y
    042C 923A      ST	R3,-Y
    042D 938A      ST	R24,-Y
    042E 939A      ST	R25,-Y
    042F B62F      IN	R2,0x3F
    0430 922A      ST	R2,-Y
(0226) 
(0227) }
(0228) 
(0229) #pragma interrupt_handler int1_isr:3
(0230) void int1_isr(void)
(0231) {//CLI();
(0232)  //external interupt on INT1
(0233) /*while(x_adc<video_x)
(0234) { v_temp[y_adc*video_x  +  x_adc] =0;x_adc++;}*/
(0235) if(xuanze++>5){xuanze=0;x_adc=0;y_adc++;}
    0431 9020012C  LDS	R2,xuanze
    0433 2433      CLR	R3
    0434 2D82      MOV	R24,R2
    0435 5F8F      SUBI	R24,0xFF
    0436 9380012C  STS	xuanze,R24
    0438 E085      LDI	R24,5
    0439 1582      CP	R24,R2
    043A F450      BCC	0x0445
    043B 2422      CLR	R2
    043C 9220012C  STS	xuanze,R2
    043E 9220012E  STS	x_adc,R2
    0440 9180012D  LDS	R24,y_adc
    0442 5F8F      SUBI	R24,0xFF
    0443 9380012D  STS	y_adc,R24
(0236) 
(0237) x_adc=video_x+1;
    0445 E281      LDI	R24,0x21
    0446 9380012E  STS	x_adc,R24
(0238) //v_num=(v_num/video_x+1)*video_x;
(0239) ms++;
    0448 91800104  LDS	R24,ms
    044A 91900105  LDS	R25,ms+1
    044C 9601      ADIW	R24,1
    044D 93900105  STS	ms+1,R25
    044F 93800104  STS	ms,R24
    0451 9029      LD	R2,Y+
    0452 BE2F      OUT	0x3F,R2
    0453 9199      LD	R25,Y+
    0454 9189      LD	R24,Y+
    0455 9039      LD	R3,Y+
    0456 9029      LD	R2,Y+
    0457 9518      RETI
(0240)  //hang=1;
(0241)  //SEI();
(0242) }
(0243) 
(0244) //TIMER0 initialize - prescale:8
(0245) // WGM: Normal
(0246) // desired value: 2uSec
(0247) // actual value:  2.000uSec (0.0%)
(0248) void timer0_init(void)
(0249) {
(0250)  TCCR0 = 0x00; //stop
_timer0_init:
    0458 2422      CLR	R2
    0459 BE23      OUT	0x33,R2
(0251)  ASSR  = 0x00; //set async mode
    045A BE20      OUT	0x30,R2
(0252)  TCNT0 = 0xFB; //set count
    045B EF8B      LDI	R24,0xFB
    045C BF82      OUT	0x32,R24
(0253)  OCR0  = 0x05;
    045D E085      LDI	R24,5
    045E BF81      OUT	0x31,R24
(0254)  TCCR0 = 0x02; //start timer
    045F E082      LDI	R24,2
    0460 BF83      OUT	0x33,R24
    0461 9508      RET
_timer0_ovf_isr:
    0462 920A      ST	R0,-Y
    0463 921A      ST	R1,-Y
    0464 922A      ST	R2,-Y
    0465 923A      ST	R3,-Y
    0466 924A      ST	R4,-Y
    0467 925A      ST	R5,-Y
    0468 926A      ST	R6,-Y
    0469 927A      ST	R7,-Y
    046A 930A      ST	R16,-Y
    046B 931A      ST	R17,-Y
    046C 932A      ST	R18,-Y
    046D 933A      ST	R19,-Y
    046E 938A      ST	R24,-Y
    046F 939A      ST	R25,-Y
    0470 93EA      ST	R30,-Y
    0471 93FA      ST	R31,-Y
    0472 B60F      IN	R0,0x3F
    0473 920A      ST	R0,-Y
(0255) }
(0256) 
(0257) #pragma interrupt_handler timer0_ovf_isr:17
(0258) void timer0_ovf_isr(void)
(0259) {
(0260)  TCNT0 = 0xFB; //reload counter value
    0474 EF8B      LDI	R24,0xFB
    0475 BF82      OUT	0x32,R24
(0261) if (  (xuanze!=0) &&  (xuanze<2)  )//滤波均值
    0476 9020012C  LDS	R2,xuanze
    0478 2022      TST	R2
    0479 F121      BEQ	0x049E
    047A 2D82      MOV	R24,R2
    047B 3082      CPI	R24,2
    047C F508      BCC	0x049E
(0262)   v_temp[y_adc][x_adc]=v_temp[y_adc][x_adc]/4+ADC/4;
    047D 9020012D  LDS	R2,y_adc
    047F E280      LDI	R24,0x20
    0480 9D82      MUL	R24,R2
    0481 0110      MOVW	R2,R0
    0482 E28F      LDI	R24,0x2F
    0483 E091      LDI	R25,1
    0484 0E28      ADD	R2,R24
    0485 1E39      ADC	R3,R25
    0486 9040012E  LDS	R4,x_adc
    0488 2455      CLR	R5
    0489 0C42      ADD	R4,R2
    048A 1C53      ADC	R5,R3
    048B E024      LDI	R18,4
    048C E030      LDI	R19,0
    048D 01F2      MOVW	R30,R4
    048E 8100      LDD	R16,Z+0
    048F 2711      CLR	R17
    0490 940E05F9  CALL	div16s
    0492 0118      MOVW	R2,R16
    0493 B064      IN	R6,0x04
    0494 B075      IN	R7,0x05
    0495 9476      LSR	R7
    0496 9467      ROR	R6
    0497 9476      LSR	R7
    0498 9467      ROR	R6
    0499 0C26      ADD	R2,R6
    049A 1C37      ADC	R3,R7
    049B 01F2      MOVW	R30,R4
    049C 8220      STD	Z+0,R2
    049D C013      RJMP	0x04B1
(0263) else /**/
(0264)   v_temp[y_adc][x_adc]=ADC>>1;
    049E 9020012D  LDS	R2,y_adc
    04A0 E280      LDI	R24,0x20
    04A1 9D82      MUL	R24,R2
    04A2 0110      MOVW	R2,R0
    04A3 E28F      LDI	R24,0x2F
    04A4 E091      LDI	R25,1
    04A5 0E28      ADD	R2,R24
    04A6 1E39      ADC	R3,R25
    04A7 91E0012E  LDS	R30,x_adc
    04A9 27FF      CLR	R31
    04AA 0DE2      ADD	R30,R2
    04AB 1DF3      ADC	R31,R3
    04AC B024      IN	R2,0x04
    04AD B035      IN	R3,0x05
    04AE 9436      LSR	R3
    04AF 9427      ROR	R2
    04B0 8220      STD	Z+0,R2
    04B1 9009      LD	R0,Y+
    04B2 BE0F      OUT	0x3F,R0
    04B3 91F9      LD	R31,Y+
    04B4 91E9      LD	R30,Y+
    04B5 9199      LD	R25,Y+
    04B6 9189      LD	R24,Y+
    04B7 9139      LD	R19,Y+
    04B8 9129      LD	R18,Y+
    04B9 9119      LD	R17,Y+
    04BA 9109      LD	R16,Y+
    04BB 9079      LD	R7,Y+
    04BC 9069      LD	R6,Y+
    04BD 9059      LD	R5,Y+
    04BE 9049      LD	R4,Y+
    04BF 9039      LD	R3,Y+
    04C0 9029      LD	R2,Y+
    04C1 9019      LD	R1,Y+
    04C2 9009      LD	R0,Y+
    04C3 9518      RETI
_main:
  n                    --> Y+2
  v_num_now            --> R10
  n_sec                --> R10
  n_juli               --> R10
  n_jiaodu             --> R10
  yv                   --> R10
  xv                   --> R12
    04C4 9721      SBIW	R28,1
(0265) }
(0266) #define PWM_ON    DDRB|=   R_pwm0 | R_pwm1 | L_pwm0 | L_pwm1;
(0267) #define PWM_OFF   DDRB&= ~(R_pwm0 | R_pwm1 | L_pwm0 | L_pwm1);
(0268) 
(0269) main()
(0270) {int n;
(0271) unsigned char n_jiaodu=0,n_juli=0;
    04C5 24AA      CLR	R10
(0272) unsigned char n_sec=0;
(0273) 
(0274) unsigned int v_num_now=0;//x_now,y_now;
    04C6 24BB      CLR	R11
(0275) unsigned char xv,yv;
(0276) 
(0277) init_devices();
    04C7 DBCA      RCALL	_init_devices
(0278) PORTD|=0x03;//外部中断
    04C8 B382      IN	R24,0x12
    04C9 6083      ORI	R24,3
    04CA BB82      OUT	0x12,R24
(0279) DDRD&=~03; 
    04CB B381      IN	R24,0x11
    04CC 7F8C      ANDI	R24,0xFC
    04CD BB81      OUT	0x11,R24
(0280) //while(1);
(0281) DDRE|=0x38;//while(1);
    04CE B182      IN	R24,0x02
    04CF 6388      ORI	R24,0x38
    04D0 B982      OUT	0x02,R24
(0282) /////////LCD
(0283) 	/* DDRB = 0xBF;    //SI输入，SO，SCK，SS输出
(0284) 	 SPCR = 0x50;  //setup SPI
(0285) 	 SPSR = 0x01;  //setup SPI*/
(0286) /*while(!(UCSR0A&(1<<UDRE0)));
(0287) UDR0='a';while(!(UCSR0A&(1<<UDRE0)));
(0288) UDR0='a';while(!(UCSR0A&(1<<UDRE0)));
(0289) UDR0='a';while(!(UCSR0A&(1<<UDRE0)));
(0290) UDR0='a';*/
(0291) delay_ms(3000);
    04D1 EB08      LDI	R16,0xB8
    04D2 E01B      LDI	R17,0xB
    04D3 940E05DD  CALL	_delay_ms
(0292) number_uart1(1010,1);
    04D5 E081      LDI	R24,1
    04D6 8388      STD	Y+0,R24
    04D7 EF02      LDI	R16,0xF2
    04D8 E013      LDI	R17,3
    04D9 E020      LDI	R18,0
    04DA E030      LDI	R19,0
    04DB DDFD      RCALL	_number_uart1
(0293) 			number_uart1(xx,0);
    04DC 2422      CLR	R2
    04DD 8228      STD	Y+0,R2
    04DE 91200108  LDS	R18,xx+2
    04E0 91300109  LDS	R19,xx+3
    04E2 91000106  LDS	R16,xx
    04E4 91100107  LDS	R17,xx+1
    04E6 DDF2      RCALL	_number_uart1
(0294) 			number_uart1(ADCjohu,1);
    04E7 E081      LDI	R24,1
    04E8 8388      STD	Y+0,R24
    04E9 91200102  LDS	R18,ADCjohu+2
    04EB 91300103  LDS	R19,ADCjohu+3
    04ED 91000100  LDS	R16,ADCjohu
    04EF 91100101  LDS	R17,ADCjohu+1
    04F1 DDE7      RCALL	_number_uart1
(0295) delay_ms(3000);	
    04F2 EB08      LDI	R16,0xB8
    04F3 E01B      LDI	R17,0xB
    04F4 940E05DD  CALL	_delay_ms
(0296) xx=0;
    04F6 E040      LDI	R20,0
    04F7 E050      LDI	R21,0
    04F8 E060      LDI	R22,0
    04F9 E070      LDI	R23,0
    04FA 93500107  STS	xx+1,R21
    04FC 93400106  STS	xx,R20
    04FE 93700109  STS	xx+3,R23
    0500 93600108  STS	xx+2,R22
(0297) //LCD_Init();
(0298) //LCD_clear();
(0299) DDRE &= ~0x7c;//if (!(PORTE & STOP))  if (!(PORTE & VOLDOWN))  if (!(PORTE & VOLUP))  if (!(PORTE & NEXTSONG))  if (!(PORTE & PREVSONG))
    0502 B182      IN	R24,0x02
    0503 7883      ANDI	R24,0x83
    0504 B982      OUT	0x02,R24
(0300) PORTE |=0x7c;
    0505 B183      IN	R24,0x03
    0506 678C      ORI	R24,0x7C
    0507 B983      OUT	0x03,R24
(0301) DDRE=0x00;PORTE=0xff;
    0508 2422      CLR	R2
    0509 B822      OUT	0x02,R2
    050A EF8F      LDI	R24,0xFF
    050B B983      OUT	0x03,R24
    050C C0BB      RJMP	0x05C8
(0302)   while(1)
(0303)   { 	   	
(0304) 			   
(0305) 	//for(xv=0;xv<video_x;xv++)		   	  
(0306)   	ADMUX = 0x01;                           // A/D converter input pin number = 0
    050D E081      LDI	R24,1
    050E B987      OUT	0x07,R24
(0307)     ADCSRA = 0xc0;//|ADATE;                           // single A/D conversion, fCK/32, conversion now started 
    050F EC80      LDI	R24,0xC0
    0510 B986      OUT	0x06,R24
(0308)     //for(y_adc=0;y_adc<video_y;y_adc++)
(0309) //while(PINE!=0xff)
(0310)  if (xuanze==0)
    0511 9020012C  LDS	R2,xuanze
    0513 2022      TST	R2
    0514 F009      BEQ	0x0516
    0515 C04C      RJMP	0x0562
(0311) {
(0312) 	for(x_adc=0;x_adc<video_x;x_adc++)
    0516 2422      CLR	R2
    0517 9220012E  STS	x_adc,R2
    0519 C043      RJMP	0x055D
(0313)     {
(0314)         do
(0315)         {
(0316) 		 //PORTE=~PORTE;
(0317)         } while(!(ADCSRA&(1<<ADIF)));// ADSC        // Wait for A/D conversion to finish
    051A 9B34      SBIS	0x06,4
    051B CFFE      RJMP	0x051A
(0318)         /*count = 6;                          
(0319)         do                                   // Customize this loop to 66 cycles !!
(0320)         {
(0321)         } while(--count);*/                   // wait some cycles
(0322)         ADCSRA |= 0x40;                      // start new A/D conversion 
    051C 9A36      SBI	0x06,6
(0323)         //write_to_flash(ADC-0x1D5);          // read data, convert to 8 bit and store in flash
(0324) 		if (  (xuanze!=0) &&  (xuanze<2)  )//滤波均值
    051D 9020012C  LDS	R2,xuanze
    051F 2022      TST	R2
    0520 F121      BEQ	0x0545
    0521 2D82      MOV	R24,R2
    0522 3082      CPI	R24,2
    0523 F508      BCC	0x0545
(0325) 		  v_temp[y_adc][x_adc]=v_temp[y_adc][x_adc]/4+ADC/4;
    0524 9020012D  LDS	R2,y_adc
    0526 E280      LDI	R24,0x20
    0527 9D82      MUL	R24,R2
    0528 0110      MOVW	R2,R0
    0529 E28F      LDI	R24,0x2F
    052A E091      LDI	R25,1
    052B 0E28      ADD	R2,R24
    052C 1E39      ADC	R3,R25
    052D 9040012E  LDS	R4,x_adc
    052F 2455      CLR	R5
    0530 0C42      ADD	R4,R2
    0531 1C53      ADC	R5,R3
    0532 E024      LDI	R18,4
    0533 E030      LDI	R19,0
    0534 01F2      MOVW	R30,R4
    0535 8100      LDD	R16,Z+0
    0536 2711      CLR	R17
    0537 940E05F9  CALL	div16s
    0539 0118      MOVW	R2,R16
    053A B064      IN	R6,0x04
    053B B075      IN	R7,0x05
    053C 9476      LSR	R7
    053D 9467      ROR	R6
    053E 9476      LSR	R7
    053F 9467      ROR	R6
    0540 0C26      ADD	R2,R6
    0541 1C37      ADC	R3,R7
    0542 01F2      MOVW	R30,R4
    0543 8220      STD	Z+0,R2
    0544 C013      RJMP	0x0558
(0326) 		else /**/
(0327) 		  v_temp[y_adc][x_adc]=ADC>>1;
    0545 9020012D  LDS	R2,y_adc
    0547 E280      LDI	R24,0x20
    0548 9D82      MUL	R24,R2
    0549 0110      MOVW	R2,R0
    054A E28F      LDI	R24,0x2F
    054B E091      LDI	R25,1
    054C 0E28      ADD	R2,R24
    054D 1E39      ADC	R3,R25
    054E 91E0012E  LDS	R30,x_adc
    0550 27FF      CLR	R31
    0551 0DE2      ADD	R30,R2
    0552 1DF3      ADC	R31,R3
    0553 B024      IN	R2,0x04
    0554 B035      IN	R3,0x05
    0555 9436      LSR	R3
    0556 9427      ROR	R2
    0557 8220      STD	Z+0,R2
    0558 9180012E  LDS	R24,x_adc
    055A 5F8F      SUBI	R24,0xFF
    055B 9380012E  STS	x_adc,R24
    055D 9180012E  LDS	R24,x_adc
    055F 3280      CPI	R24,0x20
    0560 F408      BCC	0x0562
    0561 CFB8      RJMP	0x051A
(0328) 		  
(0329)     }
(0330) }
(0331)     ADCSRA = 0x00;                           // disable AD converter
    0562 2422      CLR	R2
    0563 B826      OUT	0x06,R2
(0332) 	
(0333)   		/*if (adc1>0)