experiment_m_5a.c

利尔达TMS320F2812开发板的全套资料

//###########################################################################
//
// FILE:  experiment_m_5A.c
//
// TITLE: DSP28 T1PWM - output to generate a sine wave ,
//        GP Timer 1 Compare Interrupt every 20 mS
//        Watchdog active , served in ISR and main-loop
//
//###########################################################################

#include "DSP281x_Device.h"
#include "IQmathLib.h"
#pragma DATA_SECTION(sine_table,"IQmathTables");
_iq30 sine_table[512];


// Prototype statements for functions found within this file.

void Gpio_select(void);
//void SpeedUpRevA(void);
void InitSystem(void);
void CfgFlash(void);
interrupt void T1_Compare_isr(void);   // Prototype for GP Timer1 Compare ISR

// Global symbols defined in the linker command file

extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;

void main(void)
{
  InitSystem();                   // Initialize the DSP's core Registers

//SpeedUpRevA();                  // Speed_up the silicon A Revision.

  Gpio_select();                  // Setup the GPIO Multiplex Registers

// Copy all FLASH sections that need to run from RAM (use memcpy() from RTS library)
// Section ramfuncs contains user defined code that runs from CSM secured RAM
  memcpy( &RamfuncsRunStart,
      &RamfuncsLoadStart,
      &RamfuncsLoadEnd - &RamfuncsLoadStart);

// Initialize the FLASH
  CfgFlash();        // Initialize the FLASH

  InitPieCtrl();                  // Function Call to init PIE-unit ( code : DSP281x_PieCtrl.c)

  InitPieVectTable();             // Function call to init PIE vector table ( code : DSP281x_PieVect.c )

// re-map PIE - entry for GP Timer 1 Compare Interrupt
  EALLOW;                         // This is needed to write to EALLOW protected registers
  PieVectTable.T1CINT = &T1_Compare_isr;
  EDIS;                           // This is needed to disable write to EALLOW protected registers

// Enable T1 Compare interrupt: PIE-Group2 , interrupt 5
  PieCtrlRegs.PIEIER2.bit.INTx5=1;

// Enable CPU INT2 which is connected to GP -Timer1 Compare:
  IER = 2;

// Enable global Interrupts and higher priority real-time debug events:
  EINT;                           // Enable Global interrupt INTM
  ERTM;                           // Enable Global realtime interrupt DBGM

// Configure EVA
// Assumes EVA Clock is already enabled in InitSysCtrl();
// Drive T1PWM / T2PWM by T1/T2 - logic
  EvaRegs.GPTCONA.bit.TCMPOE = 1;
// Polarity of GP Timer 1 Compare = Active low
  EvaRegs.GPTCONA.bit.T1PIN = 1;

  EvaRegs.T1CON.bit.FREE = 0;     // Stop on emulation suspend
  EvaRegs.T1CON.bit.SOFT = 0;     // Stop on emulation suspend
  EvaRegs.T1CON.bit.TMODE = 2;    // Continuous up count mode
  EvaRegs.T1CON.bit.TPS = 0;      // prescaler = 1 : 75 MHz
  EvaRegs.T1CON.bit.TENABLE = 0;  // disable GP Timer 1 now
  EvaRegs.T1CON.bit.TCLKS10 = 0;  // internal clock
  EvaRegs.T1CON.bit.TCLD10 = 0;   // Compare Reload when zero
  EvaRegs.T1CON.bit.TECMPR = 1;   // Enable Compare operation

  EvaRegs.T1PR = 1500;
  EvaRegs.T1CMPR = EvaRegs.T1PR/2;

  EvaRegs.EVAIMRA.bit.T1CINT = 1;
  EvaRegs.T1CON.bit.TENABLE = 1;  // enable GP Timer 1 now

  while(1)
  {
    EALLOW;
    SysCtrlRegs.WDKEY = 0xAA;     // and serve watchdog #2
    EDIS;
  }
}

void Gpio_select(void)
{
  EALLOW;
  GpioMuxRegs.GPAMUX.all = 0x0;   // all GPIO port Pin's to I/O
  GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 1;  // T1PWM active
  GpioMuxRegs.GPBMUX.all = 0x0;
  GpioMuxRegs.GPDMUX.all = 0x0;
  GpioMuxRegs.GPFMUX.all = 0x0;
  GpioMuxRegs.GPEMUX.all = 0x0;
  GpioMuxRegs.GPGMUX.all = 0x0;

  GpioMuxRegs.GPADIR.all = 0x0;   // GPIO PORT  as input
  GpioMuxRegs.GPBDIR.all = 0x00FF;// GPIO Port B15-B8 input , B7-B0 output
  GpioMuxRegs.GPDDIR.all = 0x0;   // GPIO PORT  as input
  GpioMuxRegs.GPEDIR.all = 0x0;   // GPIO PORT  as input
  GpioMuxRegs.GPFDIR.all = 0x0;   // GPIO PORT  as input
  GpioMuxRegs.GPGDIR.all = 0x0;   // GPIO PORT  as input

  GpioMuxRegs.GPAQUAL.all = 0x0;  // Set GPIO input qualifier values to zero
  GpioMuxRegs.GPBQUAL.all = 0x0;
  GpioMuxRegs.GPDQUAL.all = 0x0;
  GpioMuxRegs.GPEQUAL.all = 0x0;
  EDIS;
}

/*
void SpeedUpRevA(void)
{
// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
  EALLOW;
  DevEmuRegs.M0RAMDFT = 0x0300;
  DevEmuRegs.M1RAMDFT = 0x0300;
  DevEmuRegs.L0RAMDFT = 0x0300;
  DevEmuRegs.L1RAMDFT = 0x0300;
  DevEmuRegs.H0RAMDFT = 0x0300;
  EDIS;
}
*/

void InitSystem(void)
{
  volatile int16 dummy;           // General purpose volatile int16

  EALLOW;                         // Enable EALLOW protected register access

// Memory Protection Configuration
  DevEmuRegs.PROTSTART = 0x0100;  // Write default value to protection start register
  DevEmuRegs.PROTRANGE = 0x00FF;  // Write default value to protection range register

// Unlock the Code Security Module if CSM not in use
/* Unlocking the CSM will allow code running from non-secure memory
   to access code and data in secure memory.  One would only want to
   unsecure the CSM if code security were not desired, and therefore
   the CSM is not in use (otherwise, unlocking the CSM will compromise
   the security of user code).  If the CSM is not in use, the best
   thing to do is leave the password locations programmed to 0xFFFF,
   which is the flash ERASED state.  When all passwords are 0xFFFF,
   all that is required to unlock the CSM are dummy reads of the
   PWL locations.
*/
  dummy = CsmPwl.PSWD0;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD1;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD2;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD3;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD4;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD5;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD6;           // Dummy read of PWL locations
  dummy = CsmPwl.PSWD7;           // Dummy read of PWL locations

  asm(" RPT #6 || NOP");
  
  SysCtrlRegs.WDCR= 0x00AF;       // Setup the watchdog
                                  // 0x00E8  to disable the Watchdog , Prescaler = 1
                                  // 0x00AF  to NOT disable the Watchdog, Prescaler = 64
  SysCtrlRegs.SCSR = 0;           // Watchdog generates a RESET
  SysCtrlRegs.PLLCR.bit.DIV = 10; // Setup the Clock PLL to multiply by 5

  SysCtrlRegs.HISPCP.all = 0x1;   // Setup Highspeed Clock Prescaler to divide by 2
  SysCtrlRegs.LOSPCP.all = 0x2;   // Setup Lowspeed CLock Prescaler to divide by 4

// Peripheral clock enables set for the selected peripherals.
  SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
  SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;
  SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;
  SysCtrlRegs.PCLKCR.bit.ECANENCLK=0;
  SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;
  EDIS;
}

/**********************************************************************
* Function: CfgFlash()
* Description: Initializes the F281x flash timing registers.
* Notes:
*  1) This function MUST be executed out of RAM.  Executing it out of
*     OTP/FLASH will produce unpredictable results.
*  2) The flash registers are code security module protected.  Therefore,
*     you must either run this function from L0/L1 RAM, or you must
*     first unlock the CSM.  Note that unlocking the CSM as part of
*     the program flow can compromise the code security.
*  3) The latest datasheet for the particular device of interest should
*     be consulted to confirm the flash timing specifications.
**********************************************************************/
#pragma CODE_SECTION(CfgFlash, "ramfuncs")
void CfgFlash(void)
{
  asm(" EALLOW");                      // Enable EALLOW protected register access
  FlashRegs.FPWR.bit.PWR = 3;          // Pump and bank set to active mode
  FlashRegs.FSTATUS.bit.V3STAT = 1;    // Clear the 3VSTAT bit
  FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;   // Sleep to standby transition cycles
  FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; // Standby to active transition cycles
  FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;// Random access waitstates
  FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;// Paged access waitstates
  FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;  // OTP waitstates
  FlashRegs.FOPT.bit.ENPIPE = 1;       // Enable the flash pipeline
  asm(" EDIS");                        // Disable EALLOW protected register access

// Force a complete pipeline flush to ensure that the write to the last register
// configured occurs before returning.  Safest thing is to wait 8 full cycles.

  asm(" RPT #6 || NOP");

}  //end of CfgFlash()

interrupt void T1_Compare_isr(void)
{
  static int index=0;
// Serve the watchdog every Timer 0 interrupt
  EALLOW;
  SysCtrlRegs.WDKEY = 0x55;       // Serve watchdog #1
  EDIS;
  EvaRegs.T1CMPR =  EvaRegs.T1PR - _IQsat(_IQ30mpy(sine_table[index]+_IQ30(0.9999),EvaRegs.T1PR/2),EvaRegs.T1PR,0);
  index +=4;                      // use every 4th element out of lookup table
  if (index >511) 
  	index = 0;

// Reset T1 Compare Interrupt Flag
  EvaRegs.EVAIFRA.bit.T1CINT = 1;

// Acknowledge this interrupt to receive more interrupts from group 2
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
}
//===========================================================================
// End
//===========================================================================