ad采样控制.txt

通过使用CPLD来控制AD转换,实现实时采集数据

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY ADC0809 IS       --实体名为ADC0809
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);  --IN 8位输入数据信号
CLK,EOC:IN STD_LOGIC;         --CLK 输入时钟和EOC 转换结束信号
ALE,START,OE,ADDA:OUT STD_LOGIC; --ALE锁存信号，START启动信号
-- OE 	输出容许，ADDA  
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));---Q输出数据 
END ADC0809; 

ARCHITECTURE ARC OF ADC0809 IS     --结构体说明
TYPE states IS(st0,st1,st2,st3,st4,st5,st6,st7);-- 定义状态量 
SIGNAL current_state,next_state:states:=st0; -- 状态初始化
SIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0);  --状态寄存 
SIGNAL LOCK:STD_LOGIC;  --数据锁存信号

BEGIN 
   ADDA<='1'; 
A：   PROCESS(current_state,EOC) BEGIN   -- 进程开始该进程完成AD转换的8个                                         --过程，可对照AD0809的时序图
CASE current_state IS 
WHEN st0=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<= st1; 
   -- 初始状态
WHEN st1=>ALE<='1';START<='0';OE<='0';LOCK<='0';next_state<= st2; 
  --ALE =1 选择通道
WHEN st2=>ALE<='0';START<='1';OE<='0';LOCK<='0';next_state<= st3; 
   --启动AD 
WHEN st3=>ALE<='0';START<='0';OE<='0';LOCK<='0'; 
IF(EOC='1')THEN next_state<=st3; 
  --等待转换结开始
ELSE next_state<=st4; 
END IF; 
WHEN st4=>ALE<='0';START<='0';OE<='0';LOCK<='0'; 
IF(EOC='0')THEN next_state<=st4;
   --等待转换结束 
ELSE next_state<=st5; 
END IF; 
WHEN st5=>ALE<='0';START<='0';OE<='1';LOCK<='0';next_state<= st6; 
-- 设置输出AD使能
WHEN st6=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<= st7; 
--LOCK=1，使能转换数据输出  
WHEN st7=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<= st0; 
-- 新的循环开始
WHEN OTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<= st0; 
-- 容错处理
END CASE; 
END PROCESS; 

B ：PROCESS(CLK)   -- 更新状态 BUT 时钟频率？？？
BEGIN 
IF(CLK'EVENT AND CLK='1') THEN 
current_state<=next_state; 
END IF; 
END PROCESS; 

C：PROCESS(CLK) 
BEGIN 
IF(CLK'EVENT AND CLK='1') THEN 
IF LOCK='1'THEN    --当锁存有效时输入数据
REG<=D; 
END IF; 
END IF;
END PROCESS;

Q<=REG;   -- 数据输出
END ARC;